Datasheet

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THEORY OF OPERATION
ADC SECTION
1
st
SW-CAP
Integrator
Analog
In
X(z) +
−
+
−
2
nd
SW-CAP
Integrator
3
rd
SW-CAP
Integrator
+
−
4
th
SW-CAP
Integrator
+
+
+
+
+
+
+
+
5
th
SW-CAP
Integrator
Digital
Out
Y(z)
Comparator
Qn(z)
H(z)
1-Bit
DAC
STF(z) = H(z) / [1 + H(z)]
NTF(z) = 1 / [1 + H(z)]
Y(z) = STF(z) * X(z) + NTF(z) * Qn(z)
Signal Transfer Function
Noise Transfer Function
B0005-01
DAC SECTION
PCM3000
PCM3001
SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004
The PCM3000/3001 ADC consists of a band-gap reference, a stereo single-to-differential converter, a fully
differential 5th-order delta-sigma modulator, a decimation filter (including digital high pass), and a serial interface
circuit. The block diagram in this data sheet illustrates the architecture of the ADC section. Figure 17 shows the
single-to-differential converter, and Figure 31 illustrates the architecture of the 5th-order delta-sigma modulator
and transfer functions.
An internal high-precision reference with two external capacitors provides all reference voltages required by the
ADC, which defines the full scale range for the converter. The internal single-to-differential voltage converter
saves the space and extra parts needed for external circuitry which is required by many delta-sigma converters.
The internal full-differential signal processing architecture provides a wide dynamic range and excellent power
supply rejection performance.
The input signal is sampled at a 64 × oversampling rate, eliminating the need for a sample-and-hold circuit, and
simplifying antialias filtering requirements. The 5th-order delta-sigma noise shaper consists of five integrators
which use a switched-capacitor topology, a comparator, and a feedback loop consisting of a one-bit DAC. The
delta-sigma modulator shapes the quantization noise, shifting it out of the audio band in the frequency domain.
The high order of the modulator enables it to randomize the modulator outputs, reducing idle tone levels.
The 64-f
S
1-bit data stream from the modulator is converted to 1-f
S
, 18-bit data words by the decimation filter,
which also acts as a low-pass filter to remove the shaped quantization noise. The dc components are removed
by a high-pass filter function contained within the decimation filter.
Figure 31. Simplified Fifth-Order Delta-Sigma Modulator
The delta-sigma DAC section of the PCM3000/3001 is based on a 5-level amplitude quantizer and a 3rd-order
noise shaper. This section converts the oversampled input data to a 5-level delta-sigma format. A block diagram
of the 5-level delta-sigma modulator is shown in Figure 32 . This 5-level delta-sigma modulator has the advantage
of improved stability and reduced clock-jitter sensitivity over the typical one-bit (2-level) delta-sigma modulator.
The combined oversampling rate of the delta-sigma modulator and the internal 8 × interpolation filter is 64 f
S
for a
256-f
S
system clock. The theoretical quantization noise performance of the 5-level delta-sigma modulator is
shown in Figure 33 .
32