Datasheet

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PCM3000

PCM3001

SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004

AL[7:0]: Bits 7:0 – DAC Attenuation Data for Left Channel

AL7 and AL0 are the MSB and LSB, respectively. The attenuation level (ATT) is given by

ATT = 20 × log

(AL[7:0]/256) (dB), except AL[7:0] = FFh

AL[7:0] ATTENUATION LEVEL

00h – ∞ dB (mute)

01h –48.16 dB

: :

FEh –0.07 dB

FFh 0 dB (default)

PROGRAM REGISTER 1

res: Bits 15:11 – Reserved

These bits are reserved and should be set to 0.

A[1:0]: Bits 10:9 – Register Address

These bits definte the address for REGISTER 1.

A1 A0

0 1 Register 1

LDR: Bit 8 – DAC Attenuation Data Load Control for Right Channel

This bit is used to simultaneously set the analog outputs of the left and right channels. The output

level is controlled by AR[7:0] attenuation data when this bit is set to 1. When set to 0, the new

attenuation data is stored into a register, and the output level remains at the previous attenuation

level. The LDL bit in REGISTER 0 has the equivalent function as LDR. When either LDL or LDR is

set to 1, the output levels of the left and right channels are simultaneously controlled.

AR[7:0]: Bits 7:0 – DAC Attenuation Data for Right Channel

AR7 and AR0 are the MSB and LSB, respectively. The attenuation level (ATT) is given by

ATT = 20 × log

(AR[7:0]/256) (dB), except AR[7:0] = FFh

AR[7:0] ATTENUATION LEVEL