Datasheet

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t
(CLKIH)
XTI or CLKIO
1.4 V
3.2 V
t
(CLKIL)
T0005-06
XTI
0.8 V
2.0 V
CLKIO
POWER-ON RESET
1024 System Clock Periods
Reset Reset Removal
4.4 V
4.0 V
3.6 V
V
DD
Internal Reset
System Clock
(XTI or CLKIO)
T0014-04
3 Clocks Minimum
PCM3000
PCM3001
SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004
Table 1. System Clock Frequencies
SAMPLING RATE FREQUENCY (kHz) SYSTEM CLOCK FREQUENCY (MHz)
256 f
S
384 f
S
512 f
S
32 8.1920 12.2880 16.3840
44.1 11.2896 16.9344 22.5792
48 12.2880 18.4320 24.5760
System clock pulse duration, HIGH t
(CLKIH)
12 ns (min)
System clock pulse duration, LOW t
(CLKIL)
12 ns (min)
Figure 24. External System Clock Timing
The PCM3000/3001 has internal power-on reset circuitry. Power-on reset occurs when the system clock (XTI or
CLKIO) is active and V
DD
> 4 V. For the PCM3001, the system clock must complete a minimum of 3 complete
cycles prior to V
DD
> 4 V to ensure proper reset operation. The initialization sequence requires 1024 system
cycles for completion, as shown in Figure 25 . Figure 26 shows the state of the DAC and ADC outputs during and
after the reset sequence.
Figure 25. Internal Power-On Reset Timing
24