Datasheet
PCM2704C, PCM2705C
PCM2706C, PCM2707C
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SBFS036A –AUGUST 2011–REVISED JULY 2012
SPI Register (PCM2705C/7C)
Table 14. SPI Register Description
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
0 0 0 0 ST 0 ADDR 0 D0 D1 D2 D3 D4 D5 D6 D7
D[7:0] Function of the lower 8 bits depends on the value of the ST (B11) bit.
ST = 0 (HID status write)
D7 Reports MUTE HID status to the host (active high)
D6 Reports volume-up HID status to the host (active high)
D5 Reports volume-down HID status to the host (active high)
D4 Reports next-track HID status to the host (active high)
D3 Reports previous-track HID status to the host (active high)
D2 Reports stop HID status to the host (active high)
D1 Reports play/pause HID status to the host (active high)
D0 Reports extended command status to the host (active high)
ST = 1 (ROM data write)
D[7:0] Internal descriptor ROM data, D0:LSB, D7:MSB
Contents of the power attribute and max power must be consistent with the actual application circuit
configuration (the PSEL setting and the actual power usage from V
BUS
of the USB connector); otherwise, it may
cause improper or unexpected PCM2705C/7C operation.
ADDR Starts write operation for internal descriptor reprogramming (active high)
This bit resets the descriptor ROM address counter and indicates that subsequent words should be ROM data
(described in the External ROM Example section). 456 bits of ROM data must be continuously followed after
this bit has been asserted. The data bits must be sent from LSB (D0) to MSB (D7).
To set ADDR high, ST must be set low. Note that the lower 8 bits are still active as an HID status write when
ST is set low.
Determines the function of the lower 8-bit data. Table 15 summarizes the functionality of ST
ST
and ADDR bit combinations.
0: HID status write
1: Descriptor ROM data write
Table 15. Functionality of ST and ADDR Bit Combinations
ST ADDR FUNCTION
0 0 HIS status write
0 1 HIS status write and descriptor ROM address reset
1 0 Descriptor ROM data write
1 1 Reserved
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