Datasheet

t
(SLL)
t
(SBL)
t
(SLH)
t
(SBH)
LRCK
(Output)
SYSCK
(Output)
BCK
(Output)
t
(BCH)
t
(BCL)
t
(BL)
t
(BD)
t
(LD)
t
(DH)
t
(DS)
t
(BCY)
LRCK (Output)
BCK (Output)
DOUT (Output)
DIN (Input)
50% of V
DD
50% of V
DD
50% of V
DD
50% of V
DD
PCM2704C, PCM2705C
PCM2706C, PCM2707C
www.ti.com SBFS036A –AUGUST 2011–REVISED JULY 2012
Figure 25. Audio Interface Timing
Table 9. Audio Interface Timing Characteristics
(1)
SYMBOL PARAMETER MIN MAX UNIT
t
(BCY)
BCK pulse cycle time 300 ns
t
(BCH)
BCK pulse duration, high 100 ns
t
(BCL)
BCK pulse duration, low 100 ns
t
(BL)
LRCK delay time from BCK falling edge –20 40 ns
t
(BD)
DOUT delay time from BCK falling edge –20 40 ns
t
(LD)
DOUT delay time from LRCK edge –20 40 ns
t
(DS)
DIN setup time 20 ns
t
(DH)
DIN hold time 20 ns
(1) Load capacitance of LRCK, BCK, and DOUT is 20 pF.
Figure 26. Audio Clock Timing
Table 10. Audio Clock Timing Characteristics
(1)
SYMBOL PARAMETER MIN MAX UNIT
t
(SLL)
, t
(SLH)
LRCK delay time from SYSCK rising edge –5 10 ns
t
(SBL)
, t
(SBH)
BCK delay time from SYSCK rising edge –5 10 ns
(1) Load capacitance is 20 pF.
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