Datasheet

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PCM1870
SLAS544A – MAY 2007 – REVISED SEPTEMBER 2007
MSR[2:0]: System Clock Dividing Rate Selection in Master Mode (Register 70)
Default value: 000
These bits are used to set the dividing rate of the input system clock. See Table 8 for details.
Table 8. System Clock Frequency for Common Audio Clock
REGISTER SETTING
SYSTEM CLOCK ADC SAMPLING RATE DAC SAMPLING RATE BIT CLOCK
SCK (MHz) ADC f
S
(kHz) DAC f
S
(kHz) BCK (f
S
)
MSR[2:0] NPR[5:0]
24 (SCK/256) 010 00 0000 64
16 (SCK/384) 011 00 0000 64
12 (SCK/512) 100 00 0000 64
6.144
8 (SCK/768) 101 00 0000 64
6 (SCK/1024) 110 00 0000 64
4 (SCK/1536) 111 00 0000 64
32 (SCK/256) 010 00 0000 64
8.192 16 (SCK/512) 100 00 0000 64
8 (SCK/1024) 110 00 0000 64
48 (SCK/256) 010 00 0000 64
32 (SCK/384) 011 00 0000 64
24 (SCK/512) 100 00 0000 64
12.288
16 (SCK/768) 101 00 0000 64
12 (SCK/1024) 110 00 0000 64
8 (SCK/1536) 111 00 0000 64
48 (SCK/384) 011 00 0000 64
18.432 24 (SCK/768) 101 00 0000 64
12 (SCK/1536) 111 00 0000 64
22.05 (SCK/256) 010 00 0000 64
14.7 (SCK/384) 011 00 0000 64
11.025 (SCK/512) 100 00 0000 64
5.6448
7.35 (SCK/768) 101 00 0000 64
5.5125 (SCK/1024) 110 00 0000 64
3.675 (SCK/1536) 111 00 0000 64
44.1 (SCK/256) 010 00 0000 64
29.4 (SCK/384) 011 00 0000 64
22.05 (SCK/512) 100 00 0000 64
11.2896
14.7 (SCK/768) 101 00 0000 64
11.025 (SCK/1024) 110 00 0000 64
7.35 (SCK/1536) 111 00 0000 64
NOTE: Other settings are reserved.
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