Datasheet

www.ti.com
PCM1870
SLAS544A MAY 2007 REVISED SEPTEMBER 2007
Register 79 and 80
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Register 79 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV ALV5 ALV4 ALV3 ALV2 ALV1 ALV0
Register 80 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV ARV5 ARV4 ARV3 AR2 ARV1 ARV0
IDX[6:0]: 100 1111b (4Fh) Register 79
IDX[6:0]: 101 0000b (50h) Register 80
ALV[5:0]: Gain Control for PG3 (ADC Analog Input R-Channel)
ARV[5:0]: Gain Control for PG4 (ADC Analog Input L-Channel)
Default value: 00
PG3 and PG4 can be independently controlled for ADC input from 30 dB to 12 dB in 1-dB steps. ADC output
may have zipper noise when changing levels. In the PCM1870, the noise can be reduced when making the
change by using zero-cross detection (Register 85, ZCRS).
Table 7. Gain Level Setting
ALV[5:0], ARV[5:0] ALV[5:0], ARV[5:0]
GAIN LEVEL SETTING GAIN LEVEL SETTING
BINARY HEX BINARY HEX
10 1010 2A 30 dB 01 0100 14 8 dB
10 1001 29 29 dB 01 0011 13 7 dB
10 1000 28 28 dB 01 0010 12 6 dB
10 0111 27 27 dB 01 0001 11 5 dB
10 0110 26 26 dB 01 0000 10 4 dB
10 0101 25 25 dB 00 1111 0F 3 dB
10 0100 24 24 dB 00 1110 0E 2 dB
10 0011 23 23 dB 00 1101 0D 1 dB
10 0010 22 22 dB 00 1100 0C 0 dB
10 0001 21 21 dB 00 1011 0B 1 dB
10 0000 20 20 dB 00 1010 0A 2 dB
01 1111 1F 19 dB 00 1001 09 3 dB
01 1110 1E 18 dB 00 1000 08 4 dB
01 1101 1D 17 dB 00 0111 07 5 dB
01 1100 1C 16 dB 00 0110 06 6 dB
01 1011 1B 15 dB 00 0101 05 7 dB
01 1010 1A 14 dB 00 0100 04 8 dB
01 1001 19 13 dB 00 0011 03 9 dB
01 1000 18 12 dB 00 0010 02 10 dB
01 0111 17 11 dB 00 0001 01 11 dB
01 0110 16 10 dB 00 0000 00 12 dB (default)
01 0101 15 9 dB
26 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): PCM1870