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Timing Diagram
SDA
SCL
t
(BUF)
t
(D-SU)
t
(D-HD)
Start
t
(LOW)
t
(S-HD)
t
(SCL-F)
t
(SCL-R)
t
(HI)
t
(RS-SU)
t
(RS-HD)
t
(SDA-F)
t
(SDA-R)
t
(P-SU)
Stop
t
(SP)
T0050-03
PCM1870
SLAS544A – MAY 2007 – REVISED SEPTEMBER 2007
TIMING CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN MAX UNIT
f
SCL
SCL clock frequency Standard 100 kHz
t
(BUF)
Bus free time between a STOP and START condition Standard 4.7 μ s
t
(LOW)
Low period of the SCL clock Standard 4.7 μ s
t
(HI)
High period of the SCL clock Standard 4 μ s
t
(RS-SU)
Setup time for START condition Standard 4.7 μ s
t
(S-HD)
Hold time for START condition Standard 4 μ s
t
(D-SU)
Data setup time Standard 250 ns
t
(D-HD)
Data hold time Standard 0 900 ns
t
(SCL-R)
Rise time of SCL signal Standard 20 + 0.1 C
B
1000 ns
t
(SCL-F)
Fall time of SCL signal Standard 20 + 0.1 C
B
1000 ns
t
(SDA-R)
Rise time of SDA signal Standard 20 + 0.1 C
B
1000 ns
t
(SDA-F)
Fall time of SDA signal Standard 20 + 0.1 C
B
1000 ns
t
(P-SU)
Setup time for STOP condition Standard 4 μ s
C
B
Capacitive load for SDA and SCL line 400 pF
t
(SP)
Pulse duration of spike suppressed 25 ns
Figure 23. I
2
C Interface Timing
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