Datasheet

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TWO-WIRE INTERFACE [I
2
C, MODE (PIN 28) = HIGH]
9
SDA
SCL St
Start
1−7 8 1−8 9 1−8 9 Sp
Stop
Slave Address ACK DATA ACK DATA ACK
ConditionCondition
R/W
Write Operation
Transmitter
M M M S S M S M
Data Type
St Slave Address R/W ACK ACK DATA ACK Sp
R/W
: Read Operation if 1; Otherwise, Write Operation
ACK: Acknowledgement of a Byte if 0
DATA: 8 Bits (Byte)
T0049-03
M: Master Device
St: Start Condition
M
DATA
Read Operation
Transmitter
M M M S M S M M
Data Type
St Slave Address R/W ACK ACK DATA NACK Sp
S
DATA
S: Slave Device
Sp: Stop Condition
PCM1870
SLAS544A – MAY 2007 – REVISED SEPTEMBER 2007
The PCM1870 supports the I
2
C serial bus and the data transmission protocol for the I
2
C standard as a slave
device. This protocol is explained in I
2
C specification 2.0.
In I
2
C mode, the control terminals are changed as follows.
TERMINAL NAME PROPERTY DESCRIPTION
MS/ADR Input I
2
C address
MD/SDA Input/output I
2
C data
MC/SCL Input I
2
C clock
Slave Address
MSB LSB
1 0 0 0 1 1 ADR R/ W
The PCM1870 has its 7-bit slave address. The first six bits (MSBs) of the slave address are factory preset to
1000 11. The next bit of the address byte is the device select bit, which can be user-defined by ADR terminal. A
maximum of two PCM1870s can be connected on the same bus at one time. Each PCM1870 responds when it
receives its own slave address.
Packet Protocol
A master device must control packet protocol, which is start condition, slave address with read/write bit, data if
write or acknowledgement if read, and stop condition. The PCM1870 supports only slave-receiver and
slave-transmitter.
Figure 20. Basic I
2
C Framework
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