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Three-Wire Interface (SPI) Timing Requirements
t
w(MCH)
50%ofV
IO
MS
t
(MLS)
LSB
50%ofV
IO
50%ofV
IO
t
w(MCL)
t
w(MHH)
t
(MLH)
t
(MCY)
t
(MDH)
t
(MDS)
MC
MD
T0013-08
PCM1870
SLAS544A – MAY 2007 – REVISED SEPTEMBER 2007
Figure 19 shows a detailed timing diagram for the serial control interface. These timing parameters are critical for
proper control port operation.
PARAMETERS SYMBOL MIN TYP MAX UNIT
MC pulse cycle time t
(MCY)
500
(1)
ns
MC low-level time t
w(MCL)
50 ns
MC high-level time t
w(MCH)
50 ns
MS high-level time t
w(MHH)
See
(1)
ns
MS falling edge to MC rising edge t
(MLS)
50 ns
MS hold time t
(MLH)
20 ns
MD hold time t
(MDH)
15 ns
MD setup time t
(MDS)
20 ns
(1) 3/(128 f
S
) s (min), where f
S
is the sampling frequency
A
Figure 19. SPI Interface Timing
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