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TIMING DIAGRAM
SDA
SCL
t
(BUF)
t
(D-SU)
t
(D-HD)
Start
t
(LOW)
t
(S-HD)
t
(SCL-F)
t
(SCL-R)
t
(HI)
Repeated Start
t
(RS-SU)
t
(RS-HD)
t
(SDA-F)
t
(SDA-R)
t
(P-SU)
Stop
T0050-01
PCM1850A
PCM1851A
SLES173 – MARCH 2006
SYMBOL PARAMETER MIN MAX UNIT
f
(SCL)
SCL clock frequency 100 kHz
t
(BUF)
Bus free time between STOP and START conditions 4.7 µ s
t
(LOW)
Low period of the SCL clock 4.7 µ s
t
(HI)
High period of the SCL clock 4 µ s
t
(RS-SU)
Setup time for START/repeated START condition 4.7 µ s
t
(S-HD)
, t
(RS-HD)
Hold time for START/repeated START condition 4 µ s
t
(D-SU)
Data setup time 250 ns
t
(D-HD)
Data hold time 0 900 ns
t
(SCL-R)
Rise time of SCL signal 20 + 0.1 C
B
1000 ns
t
(SCL-F)
Fall time of SCL signal 20 + 0.1 C
B
1000 ns
t
(SDA-R)
Rise time of SDA signal 20 + 0.1 C
B
1000 ns
t
(SDA-F)
Fall time of SDA signal 20 + 0.1 C
B
1000 ns
t
(P-SU)
Setup time for STOP condition 4 µ s
C
B
Capacitive load for SDA and SCL lines 400 pF
V
NH
Noise margin at HIGH level for each connected device (including hysteresis) 0.2 V
DD
V
Figure 32. PCM1851A Control Interface Timing Requirements
26
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