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CONTROL INTERFACE TIMING REQUIREMENTS (PCM1850A)
t
(MCH)
1.4 V
MS
t
(MSS)
LSB
1.4 V
1.4 V
t
(MCL)
t
(MHH)
t
(MSH)
t
(MCY)
t
(MDH)
t
(MDS)
MC
MD
T0013-06
I
2
C SERIAL CONTROL PORT FOR MODE CONTROL (PCM1851A)
Slave Address
Packet Protocol
PCM1850A
PCM1851A
SLES173 – MARCH 2006
Figure 29 shows a detailed timing diagram for the serial control interface of the PCM1850A. These timing
parameters are critical for proper control port operation.
SYMBOL PARAMETER MIN MAX UNIT
t
(MCY)
MC pulse cycle time 100 ns
t
(MCL)
MC LOW-level time 40 ns
t
(MCH)
MC HIGH-level time 40 ns
t
(MHH)
MS HIGH-level time 80 ns
t
(MSS)
MS falling edge to MC rising edge 15 ns
t
(MSH)
MS hold time
(1)
15 ns
t
(MDH)
MD hold time 15 ns
t
(MDS)
MD setup time 15 ns
(1) MC rising edge for LSB to MS rising edge
Figure 29. PCM1850A Control Interface Timing
The user-programmable built-in function of the PCM1851A can be controlled through the I
2
C-format serial control
port, SDA (pin 32) and SCL (pin 31). The PCM1851A supports the I
2
C serial bus and the data transmission
protocol for standard mode as a slave device. This protocol is explained in I
2
C specification 2.0.
MSB LSB
1 0 0 1 0 1 ADR R/nW
The PCM1851A has 7 bits for its own slave address. The first six bits (MSBs) of the slave address are factory
preset to 100101. The last bit of the address byte is the device select bit, which can be user-defined by the ADR
pin (pin 30). A maximum of two PCM1851As can be connected on the same bus at one time. Each PCM1851A
responds when it receives its own slave address.
A master device must control packet protocol, which consists of start condition, slave address with read/write bit,
data if write or acknowledgement if read, and stop condition. The PCM1851A supports only slave receivers, so
the R/ W bit must be set to 0.
24
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