Datasheet

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Interface Timing
BCK
LRCK
DOUT
t
(BCKH)
t
(BCKL)
t
(LRHD)
t
(LRCP)
t
(LRSU)
t
(BCKP)
t
(CKDO)
t
(LRDO)
1.4 V
1.4 V
0.5 V
DD
T0017-02
PCM1850A
PCM1851A
SLES173 – MARCH 2006
Figure 24 and Figure 25 illustrate the interface timing in slave and master modes, respectively.
SYMBOL PARAMETER MIN TYP MAX UNIT
t
(BCKP)
BCK period 150 ns
t
(BCKH)
BCK pulse duration, HIGH 60 ns
t
(BCKL)
BCK pulse duration, LOW 60 ns
t
(LRSU)
LRCK setup time to BCK rising edge 20 ns
t
(LRHD)
LRCK hold time to BCK rising edge 20 ns
t
(LRCP)
LRCK period 10 µ s
t
(CKDO)
Delay time, BCK falling edge to DOUT valid –10 20 ns
t
(LRDO)
Delay time, LRCK edge to DOUT valid –10 20 ns
t
r
Rise time of all signals 10 ns
t
f
Fall time of all signals 10 ns
NOTE: Timing measurement reference level is 1.4 V for input and 0.5 V
DD
for output. Rise and fall times are measured from 10% to 90% of
IN/OUT signal swing. Load capacitance of DOUT is 20 pF.
Figure 24. Audio Data Interface Timing (Slave Mode: LRCK, BCK Work as Inputs)
20
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