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SERIAL AUDIO DATA INTERFACE
Interface Mode
Data Format
PCM1850A
PCM1851A
SLES173 – MARCH 2006
The PCM1850A/1851A interfaces with the audio system through BCK (pin 2), LRCK (pin 1), and DOUT (pin 3).
The PCM1850A/1851A supports both master and slave modes as interface modes, and they are selected by
mode control via the serial port as shown in Table 4 .
In master mode, the PCM1850A/1851A provides the timing for serial audio data communications between the
PCM1850A/1851A and the digital audio processor or external circuit. While in slave mode, the PCM1850A/1851A
receives the timing for data transfer from an external controller.
Table 4. Interface Mode
MD1 MD0 INTERFACE MODE
0 0 Slave mode (256 f
S
, 384 f
S
, 512 f
S
, 768 f
S
) (default)
0 1 Master mode (256 f
S
)
1 0 Master mode (384 f
S
)
1 1 Master mode (512 f
S
)
Master Mode
In master mode, BCK and LRCK work as output pins, and these pins are controlled by timing which is generated
in the clock and timing control circuit of the PCM1850A/1851A. The frequency of BCK is fixed at 64 × LRCK. A
768-f
S
system clock is not available in master mode.
Slave Mode
In slave mode, BCK and LRCK work as input pins. The PCM1850A/1851A accepts the 64 BCK/LRCK or 48
BCK/LRCK (only for 384 f
S
SCKI) format. A 768-f
S
system clock is not available for f
S
= 88.2 kHz and 96 kHz in
slave mode.
The PCM1850A/1851A supports four audio data formats in both master and slave modes, and they are selected
by mode control via the serial port as shown in Table 5 . Figure 23 illustrates the data formats in both slave and
master modes.
Table 5. Data Format
FORMAT NO. FMT2 FMT1 FMT0 FORMAT
0 1 0 1 Left-justified, 24-bit
1 1 0 0 I
2
S, 24-bit, (default)
2 0 0 0 Right-justified, 24-bit
3 0 1 1 Right-justified, 16-bit
18
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