Datasheet

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DETAILED DESCRIPTION
SYSTEM CLOCK
t
(SCKH)
SCKI
t
(SCKL)
2 V
0.8 V
H
L
T0005-11
PCM1850A
PCM1851A
SLES173 – MARCH 2006
The PCM1850A/1851A supports 256 f
S
, 384 f
S
, 512 f
S
, and 768 f
S
as the system clock, where f
S
is the audio
sampling frequency. The system clock must be supplied on SCKI (pin 7).
The PCM1850A/1851A has a system clock detection circuit which automatically senses if the system clock is
operating at 256 f
S
, 384 f
S
, 512 f
S
, or 768 f
S
in slave mode. In master mode, the system clock frequency must be
selected by mode control via the serial port. The 768-f
S
system clock is not available in master mode or for f
S
=
88.2 kHz and 96 kHz in the slave mode. The system clock is divided into 128 f
S
and 64 f
S
automatically, and
these frequencies are used to operate the digital filter and the delta-sigma modulator, respectively.
Table 1 shows the relationship of typical sampling frequency to system clock frequency, and Figure 20 shows
system clock timing.
Table 1. Sampling Frequency and System Clock Frequency
SYSTEM CLOCK FREQUENCY (MHz)
SAMPLING RATE FREQUENCY
(kHz)
256 f
S
384 f
S
512 f
S
768 f
S
(1)
32 8.192 12.288 16.384 24.576
44.1 11.2896 16.9344 22.5792 33.8688
48 12.288 18.432 24.576 36.864
64 16.384 24.576 32.768 49.152
88.2 22.5792 33.8688 45.1584 —
96 24.576 36.864 49.152 —
(1) Slave mode only
SYMBOL PARAMETER MIN MAX UNIT
t
(SCKH)
System clock pulse duration, HIGH 8 ns
t
(SCKL)
System clock pulse duration, LOW 8 ns
Figure 20. System Clock Timing
14
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