Datasheet

www.ti.com
CLOCK-HALT POWER-DOWN AND RESET FUNCTION
Clock-Halt Reset
SCKI
T0081-01
48/f
in
or 48/f
S
Fade-In Start
Fade-In Complete
Internal
Reset
Operation Operation
DOUT Normal Data Normal Data
DOUT
(Contents)
Normal Data
SCKI Halt SCKI Resume
Fixed to Low or High
t
(CKR)
Reset: t
(RST)
Reset Release: t
(REL)
BPZ
Zero Data
PCM1808
SLES177A – APRIL 2006 – REVISED AUGUST 2006
The PCM1808 has a power-down and reset function, which is triggered by halting SCKI (pin 6) in both master
and slave modes. The function is available anytime after power on. Reset and power down are performed
automatically 4 µ s (minimum) after SCKI is halted. While the clock-halt reset is asserted, the PCM1808 stays in
the reset and power-down mode, and DOUT (pin 9) is forced to zero. SCKI must be supplied to release the
reset and power-down mode. The digital output is valid after the reset state is released and the time of 1024
SCKI + 8960/f
S
has elapsed. Because the fade-in operation is performed, it takes additional time of 48/f
in
or
48/f
S
until the level corresponding to the analog input signal is obtained. Figure 20 illustrates the clock-halt reset
timing.
To avoid ADC performance degradation, BCK (pin 8) and LRCK (pin 7) are required to synchronize with SCKI
within 4480/f
S
after SCKI is resumed. If it takes more than 4480/f
S
for BCK and LRCK to synchronize with SCKI,
SCKI should be masked until the synchronization is achieved again, taking care of glitch and jitter. See the
typical circuit connection diagram, Figure 26 .
To avoid ADC performance degradation, the clock-halt reset also should be asserted when system clock SCKIor
the audio interface clocks BCK and LRCK (sampling rate f
S
) are changed on the fly.
SYMBOL PARAMETER MIN MAX UNIT
t
(CKR)
Delay time from SCKI halt to internal reset 4 µ s
t
(RST)
Delay time from SCKI resume to reset release 1024 SCKI µ s
t
(REL)
Delay time from reset release to DOUT output 8960/f
S
µ s
Figure 20. Clock-Halt Power-Down and Reset Timing
13
Submit Documentation Feedback