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FEATURES APPLICATIONS

DESCRIPTION

PCM1808

SLES177A – APRIL 2006 – REVISED AUGUST 2006

SINGLE-ENDED, ANALOG-INPUT 24-BIT, 96-kHz STEREO A/D CONVERTER

• DVD Recorder

• 24-Bit Delta-Sigma Stereo A/D Converter

• Digital TV

• Single-Ended Voltage Input: 3 Vp-p

• AV Amplifier/Receiver

• High Performance:

• MD Player

– THD + N: –93 dB (Typical)

• CD Recorder

– SNR: 99 dB (Typical)

• Multitrack Receiver

– Dynamic Range: 99 dB (Typical)

• Electric Musical Instrument

• Oversampling Decimation Filter:

– Oversampling Frequency: × 64

– Pass-Band Ripple: ±0.05 dB

The PCM1808 is high-performance, low-cost,

– Stop-Band Attenuation: –65 dB

single-chip, stereo analog-to-digital converter with

single-ended analog voltage input. The PCM1808

– On-Chip High-Pass Filter: 0.91 Hz (48 kHz)

uses a delta-sigma modulator with 64-times

• Flexible PCM Audio Interface

oversampling and includes a digital decimation filter

– Master/Slave Mode Selectable

and high-pass filter that removes the dc component

of the input signal. For various applications, the

– Data Formats: 24-Bit I

S, 24-Bit

PCM1808 supports master and slave mode and two

Left-Justified

data formats in serial audio interface.

• Power Down and Reset by Halting System

The PCM1808 supports the power-down and reset

Clock

function by means of halting the system clock.

• Analog Antialias LPF Included

The PCM1808 is suitable for wide variety of

• Sampling Rate: 8 kHz–96 kHz

cost-sensitive consumer applications where good

• System Clock: 256 f

, 384 f

, 512 f

performance and operation with a 5-V analog supply

• Dual Power Supplies:

and 3.3-V digital supply is required. The PCM1808 is

fabricated using a highly advanced CMOS process

– 5-V for Analog

and is available in a small, 14-pin TSSOP package.

– 3.3-V for Digital

• Package: 14-Pin TSSOP

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

System Two, Audio Precision are trademarks of Audio Precision, Inc.

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (27 pages)

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PCM1808 SLES177A – APRIL 2006 – REVISED AUGUST 2006 SINGLE-ENDED, ANALOG-INPUT 24-BIT, 96-kHz STEREO A/D CONVERTER FEATURES APPLICATIONS • • • • • • • • • • • • • • • • • • 24-Bit Delta-Sigma Stereo A/D Converter Single-Ended Voltage Input: 3 Vp-p High Performance: – THD + N: –93 dB (Typical) – SNR: 99 dB (Typical) – Dynamic Range: 99 dB (Typical) Oversampling Decimation Filter: – Oversampling Frequency: ×64 – Pass-Band Ripple: ±0.
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PCM1808 www.ti.com SLES177A – APRIL 2006 – REVISED AUGUST 2006 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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PCM1808 www.ti.com SLES177A – APRIL 2006 – REVISED AUGUST 2006 ELECTRICAL CHARACTERISTICS All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 512 fS, 24-bit data, unless otherwise noted PARAMETER TEST CONDITIONS MIN Resolution TYP MAX 24 UNIT Bits DATA FORMAT I2S, left-justified Audio data interface format Audio data bit length 24 Audio data format fS Sampling frequency System clock frequency Bits MSB-first, 2s complement 8 48 96 256 fS 2.
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PCM1808 www.ti.com SLES177A – APRIL 2006 – REVISED AUGUST 2006 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 512 fS, 24-bit data, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUT Input voltage 0.6 VCC Center voltage (VREF) 0.5 VCC Input impedance Antialiasing filter frequency response –3 dB Vp-p V 60 kΩ 1.3 MHz DIGITAL FILTER PERFORMANCE Pass band 0.
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PCM1808 www.ti.
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PCM1808 www.ti.com SLES177A – APRIL 2006 – REVISED AUGUST 2006 Functional Block Diagram Antialias LPF VINL VREF Delta-Sigma Modulator BCK ×1/64 Decimation Filter with High-Pass Filter Reference Antialias LPF VINR DOUT FMT Mode/ Format Control MD1 Delta-Sigma Modulator MD0 Clock and Timing Control Power Supply VCC LRCK Serial Interface AGND DGND SCKI VDD B0004-10 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS All specifications at TA = 25°C, VCC = 5 V, VDD = 3.
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PCM1808 www.ti.com SLES177A – APRIL 2006 – REVISED AUGUST 2006 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (Continued) All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 512 fS, 24-bit data, unless otherwise noted. DECIMATION FILTER FREQUENCY RESPONSE (Continued) PASS-BAND RIPPLE CHARACTERISTICS TRANSITION BAND CHARACTERISTICS 0.2 0 −1 −2 −3 −0.2 Amplitude − dB Amplitude − dB 0.0 −0.4 −0.6 −4 –4.13 dB at 0.5 fS −5 −6 −7 −8 −0.8 −9 −1.0 0.0 0.
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PCM1808 www.ti.com SLES177A – APRIL 2006 – REVISED AUGUST 2006 TYPICAL PERFORMANCE CURVES All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 512 fS, 24-bit data, unless otherwise noted.
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PCM1808 www.ti.com SLES177A – APRIL 2006 – REVISED AUGUST 2006 TYPICAL PERFORMANCE CURVES (Continued) All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 512 fS, 24-bit data, unless otherwise noted.
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PCM1808 www.ti.com SLES177A – APRIL 2006 – REVISED AUGUST 2006 TYPICAL PERFORMANCE CURVES (Continued) All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 512 fS, 24-bit data, unless otherwise noted. OUTPUT SPECTRUM (Continued) THD + N − Total Harmonic Distortion + Noise − dB THD + N vs SIGNAL LEVEL 0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0 Signal Level − dB G015 Figure 15.
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PCM1808 www.ti.com SLES177A – APRIL 2006 – REVISED AUGUST 2006 SYSTEM CLOCK The PCM1808 supports 256 fS, 384 fS and 512 fS as system clock, where fS is the audio sampling frequency. The system clock must be supplied on SCKI (pin 6). The PCM1808 has a system clock detection circuit which automatically senses if the system clock is operating at 256 fS, 384 fS, or 512 fS in slave mode.
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PCM1808 www.ti.com SLES177A – APRIL 2006 – REVISED AUGUST 2006 Fade-Out Start Fade-In Complete Fade-In Start DOUT (Contents) Fade-Out Complete BPZ 48/fin or 48/fS 48/fin or 48/fS T0080-01 Figure 18. Fade-In and Fade-Out Operations POWER ON The PCM1808 has an internal power-on-reset circuit, and initialization (reset) is performed automatically when the power supply (VDD) exceeds 2.2 V (typical). While VDD < 2.2 V (typical), and for 1024 system-clock counts after VDD > 2.
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PCM1808 www.ti.com SLES177A – APRIL 2006 – REVISED AUGUST 2006 CLOCK-HALT POWER-DOWN AND RESET FUNCTION The PCM1808 has a power-down and reset function, which is triggered by halting SCKI (pin 6) in both master and slave modes. The function is available anytime after power on. Reset and power down are performed automatically 4 µs (minimum) after SCKI is halted. While the clock-halt reset is asserted, the PCM1808 stays in the reset and power-down mode, and DOUT (pin 9) is forced to zero.
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PCM1808 www.ti.com SLES177A – APRIL 2006 – REVISED AUGUST 2006 SERIAL AUDIO DATA INTERFACE The PCM1808 interfaces the audio system through LRCK (pin 7), BCK (pin 8), and DOUT (pin 9). INTERFACE MODE The PCM1808 supports master mode and slave mode as interface modes, which are selected by MD1 (pin 11) and MD0 (pin 10), as shown in Table 2. MD1 and MD0 must be set prior to power on.
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PCM1808 www.ti.com SLES177A – APRIL 2006 – REVISED AUGUST 2006 FORMAT 0: FMT = LOW 24-Bit, MSB-First, I2S Left-Channel LRCK Right-Channel BCK DOUT 1 2 3 22 23 24 MSB 1 LSB 2 3 22 23 24 MSB LSB FORMAT 1: FMT = HIGH 24-Bit, MSB-First, Left-Justified Left-Channel LRCK Right-Channel BCK DOUT 1 2 MSB 3 22 23 24 LSB 1 2 3 MSB 22 23 24 1 LSB T0016-17 Figure 21.
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PCM1808 www.ti.com SLES177A – APRIL 2006 – REVISED AUGUST 2006 INTERFACE TIMING Figure 22 and Figure 23 illustrate the interface timing in slave mode and master mode, respectively. t(LRCP) 1.4 V LRCK t(BCKL) t(LRSU) t(BCKH) t(LRHD) 1.4 V BCK t(CKDO) t(BCKP) t(LRDO) 0.5 VDD DOUT T0017-02 SYMBOL PARAMETER t(BCKP) BCK period t(BCKH) t(BCKL) t(LRSU) MIN TYP MAX UNIT 1/(64 fS) ns BCK pulse duration, HIGH 1.5 × t(SCKI) ns BCK pulse duration, LOW 1.
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PCM1808 www.ti.com SLES177A – APRIL 2006 – REVISED AUGUST 2006 t(LRCP) 0.5 VDD LRCK t(BCKL) t(BCKH) t(CKLR) 0.5 VDD BCK t(CKDO) t(BCKP) t(LRDO) 0.
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PCM1808 www.ti.com SLES177A – APRIL 2006 – REVISED AUGUST 2006 SYNCHRONIZATION WITH DIGITAL AUDIO SYSTEM In slave mode, the PCM1808 operates under LRCK (pin 7), synchronized with system clock SCKI (pin 6). The PCM1808 does not require a specific phase relationship between LRCK and SCKI, but does require the synchronization of LRCK and SCKI.
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PCM1808 www.ti.com SLES177A – APRIL 2006 – REVISED AUGUST 2006 APPLICATION INFORMATION TYPICAL CIRCUIT CONNECTION DIAGRAM Figure 26 is a typical circuit connection diagram. The antialiasing low-pass filters are integrated on the analog inputs, VINL and VINR. If the performance of these filters is not adequate for an application, appropriate external antialiasing filters are needed. A passive RC filter (100 Ω and 0.01 µF to 1 kΩ and 1000 pF) generally is used. PCM1808 C5(3) C4(2) 4 µs (min) 5V 3.
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PCM1808 www.ti.com SLES177A – APRIL 2006 – REVISED AUGUST 2006 APPLICATION INFORMATION (continued) VREF PIN To ensure low source impedance of the ADC references, 0.1-µF ceramic and 10-µF electrolytic capacitors are recommended between VREF and AGND. These capacitors should be located as close as possible to the VREF pin to reduce dynamic errors on the ADC references.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device PCM1808PWR Package Package Pins Type Drawing TSSOP PW 14 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 12.4 Pack Materials-Page 1 6.9 B0 (mm) K0 (mm) P1 (mm) 5.6 1.6 8.0 W Pin1 (mm) Quadrant 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PCM1808PWR TSSOP PW 14 2000 367.0 367.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.