Datasheet

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V
REF
PIN
DOUT PIN
SYSTEM CLOCK
PCM1807
SLES147 – SEPTEMBER 2005
APPLICATION INFORMATION (continued)
To ensure low source impedance of the ADC references, 0.1- µ F ceramic and 10- µ F electrolytic capacitors are
recommended between V
REF
and AGND. These capacitors should be located as close as possible to the V
REF
pin to reduce dynamic errors on the ADC references.
The DOUT pin has a large load-drive capability, but if the DOUT line is long, locating a buffer near the PCM1807
and minimizing load capacitance is recommended to minimize the digital-analog crosstalk and maximize the
dynamic performance of the ADC.
The quality of the system clock can influence dynamic performance, as the PCM1807 operates based on a
system clock. Therefore, it may be necessary to consider the system clock duty, jitter, and the time difference
between system clock transition and BCK or LRCK transition in slave mode.
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