Datasheet

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SYSTEM RESET
T0084-01
48/f
in
or 48/f
S
Fade-In Start
Fade-In Complete
DOUT
DOUT
(Contents)
Reset: t
(RST)
Reset Release: t
(REL)
Zero Data
SCKI
SRST
Internal
Reset
Normal Data Normal Data
Normal Data
BPZ
PCM1807
SLES147 – SEPTEMBER 2005
The SRST bit controls the entire ADC operation except fade-out. DOUT is forced to zero immediately and the
PCM1807 goes into power-down state. Also, all registers except the mode control register are reset once. The
PCM1807 minimizes power dissipation during the power-down state. When the PCM1807 powers up, the digital
output is valid after the reset state is released and the time of 1024 SCKI + 8960/f
S
has elapsed. Because the
fade-in operation is performed, it takes additional time of 48/f
in
or 48/f
S
until the level corresponding to the analog
input signal is obtained. Figure 27 illustrates DOUT behavior during the power-down and power-up sequences by
SRST.
SYMBOL PARAMETER MIN MAX UNIT
t
(RST)
Delay time from SCKI resume to reset release 1024 SCKI µ s
t
(REL)
Delay time from reset release to DOUT output 8960/f
S
µ s
Figure 27. Power-Up/Power-Down Sequence by SRST
Table 8. System Reset Control
SRST SYSTEM RESET
0 System reset
1 Normal operation (default)
21