Datasheet

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POWER DOWN
T0083-01
48/f
in
or 48/f
S
Fade-In Start
Fade-In Complete
DOUT
DOUT
(Contents)
Reset: t
(RST)
Zero Data
SCKI
PDWN
Internal
Reset
Normal Data
Operation
Normal Data
BPZ
48/f
in
or 48/f
S
Fade-Out Start
Fade-Out Complete
Normal Data
Reset Release: t
(REL)
PCM1807
SLES147 – SEPTEMBER 2005
The PDWN bit controls the operation of the PCM1807. During power-down mode, both supply current for the
analog section and clock signal for the digital section are shut down, and DOUT is forced to zero. Also, all
registers except the mode control registers are reset once. The PCM1807 minimizes power dissipation during the
power-down mode. When the PCM1807 takes power down or power up, fade-out or fade-in which is shown in
Figure 18 is asserted, respectively. The system clock must be input until the fade-out process completes and
prior to PDWN deassertion. The digital output is valid after the reset state is released and the time of 1024 SCKI
+ 8960/f
S
has elapsed. Because the fade-in operation is processed, it takes additional time of 48/f
in
or 48/f
S
until
the level corresponding to the analog input signal is obtained. Figure 26 illustrates DOUT behavior on the
power-down and power-up sequence by PDWN.
SYMBOL PARAMETER MIN MAX UNIT
t
(RST)
Delay time from SCKI resume to reset release 1024 SCKI µ s
t
(REL)
Delay time from reset release to DOUT output 8960/f
S
µ s
Figure 26. Power Up/Power Down Sequence by PDWN
Table 7. Power-Down Control
PDWN POWER DOWN
0 Normal operation (default)
1 Power-down mode
20