Datasheet

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SYNCHRONIZATION WITH DIGITAL AUDIO SYSTEM
32/f
S
T0082-01
48/f
in
or 48/f
S
Fade-In Start
Fade-In Complete
DOUT
DOUT
(Contents)
Normal Data
Synchronization Lost
Synchronous
1/f
S
BPZ
State of
Synchronization
Asynchronous Synchronous
Resynchronization
Synchronization Lost
Asynchronous
Resynchronization
Synchronous
Normal Data
Undefined
Data
Normal DataZero Data Zero Data Normal Data
48/f
in
or 48/f
S
Fade-In Restart
32/f
S
PCM1807
SLES147 – SEPTEMBER 2005
In slave mode, the PCM1807 operates under LRCK, synchronized with system clock SCKI. The PCM1807 does
not require a specific phase relationship between LRCK and SCKI, but does require the synchronization of LRCK
and SCKI.
If the relationship between LRCK and SCKI changes more than ±6 BCKs for 64 BCK/frame (±5 BCKs for 48
BCK/frame) during one sample period due to LRCK or SCKI jitter, internal operation of the ADC halts within 1/f
S
and digital output is forced to zero data (BPZ code) until resynchronization between LRCK and SCKI is
established.
In the case of changes less than ±5 BCKs for 64 BCK/frame (±4 BCKs for 48 BCK/frame), resynchronization
does not occur and the previously described digital output control and discontinuity do not occur.
Figure 25 illustrates the digital output response for loss of synchronization and resynchronization. During
undefined data, the PCM1807 can generate some noise in the audio signal. Also, the transition of normal data to
undefined data creates a discontinuity in the digital output data, which can generate some noise in audio signal.
The digital output is valid after resynchronization completes and the time of 32/f
S
has elapsed. Because the
fade-in operation is performed, it takes additional time of 48/f
in
or 48/f
S
until the level corresponding to the analog
input signal is obtained. If synchronization is lost during the fade-in or fade-out operation, the operation stops and
DOUT is forced to zero data immediately. The fade-in operation resumes from mute after the time of 32/f
S
following resynchronization.
It is recommended to set the PDWN bit to HIGH once through the serial control port to get stable analog
performance when the sampling rate, interface mode, or data format is changed.
Figure 25. ADC Digital Output for Loss of Synchronization and Resynchronization
18