Datasheet

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BPZ
Fade-In Start
DOUT
(Contents)
T0080-01
Fade-In Complete
48/f
in
or 48/f
S
48/f
in
or 48/f
S
Fade-Out Start
Fade-Out Complete
POWER ON
1024 System Clocks
Reset Reset Release
2.6 V
2.2 V
1.8 V
V
DD
Internal
Reset
System
Clock
DOUT
Zero Data Normal Data
T0014-09
8960/f
S
48/f
in
or 48/f
S
Fade-In Start
Fade-In Complete
Operation
DOUT
(Contents)
BPZ
PCM1807
SLES147 – SEPTEMBER 2005
Figure 18. Fade-In and Fade-Out Operations
The PCM1807 has an internal power-on-reset circuit, and initialization (reset) is performed automatically when
the power supply (V
DD
) exceeds 2.2 V (typical). While V
DD
< 2.2 V (typical), and for 1024 system-clock counts
after V
DD
> 2.2 V (typical), the PCM1807 stays in the reset state and the digital output is forced to zero. The
digital output is valid after the reset state is released and the time of 8960/f
S
has elapsed. Because the fade-in
operation is performed, it takes additional time of 48/f
in
or 48/f
S
until the data corresponding to the analog input
signal is obtained. Figure 19 illustrates the power-on timing and the digital output.
Figure 19. Power-On Timing
12