Datasheet

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ELECTRICAL CHARACTERISTICS
PCM1804
SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007
All specifications at T
A
= 25 ° C, V
CC
= 5 V, V
DD
= 3.3 V, master mode, single-speed mode, f
S
= 48 kHz, system clock = 256 f
S
,
24-bit data, unless otherwise noted.
PCM1804DB
PARAMETER TEST CONDITIONS UNIT
MIN TYP MAX
Resolution 24 Bits
DATA FORMAT
Audio data interface format Standard, I
2
S, left-justified
Audio data bit length 24 Bits
MSB first,
Audio data format
2s complement, DSD
DIGITAL INPUT/OUTPUT
Logic family TTL compatible
(1) (2)
2 5.5
V
IH
High-level input voltage Vdc
(3)
2 V
DD
V
IL
Low-level input voltage
(1) (2) (3)
0.8 Vdc
V
IN
= V
DD
(1)
65 100
I
IH
High-level input current V
IN
= V
DD
(2)
± 10 μ A
V
IN
= V
DD
(3)
± 100
V
IN
= 0 V
(1) (2)
± 10
I
IL
Low-level input current μ A
V
IN
= 0 V
(3)
± 50
V
OH
High-level output voltage I
OH
= – 1 mA
(4)
2.4 Vdc
V
OL
Low-level output voltage I
OL
= 1 mA
(4)
0.4 Vdc
CLOCK FREQUENCY
f
S
Sampling frequency 32 192 kHz
256 f
S
, single rate
(5)
12.288
384 f
S
, single rate
(5)
18.432
512 f
S
, single rate
(5)
24.576
768 f
S
, single rate
(5)
36.864
System clock frequency MHz
256 f
S
, dual rate
(6)
24.576
384 f
S
, dual rate
(6)
36.864
128 f
S
, quad rate
(7)
24.576
192 f
S
, quad rate
(7)
36.864
DC ACCURACY
Gain mismatch, channel-
± 3 % of FSR
to-channel
Gain error (V
IN
= – 0.5 dB) ± 4 % of FSR
Bipolar zero error HPF bypass ± 0.2 % of FSR
(1) Pins 6 – 11, 19: FMT0, FMT1, S/ M, OSR0, OSR1, OSR2, RST [Schmitt-trigger input with internal pulldown (51 k μ typically), 5-V tolerant]
(2) Pin 18: SCKI (Schmitt-trigger input, 5-V tolerant)
(3) Pins 12, 16 – 17: BYPAS, BCK/DSDL, LRCK/DSDBCK (in slave mode, Schmitt-trigger input)
(4) Pins 15 – 17, 20, and 21: DATA/DSDR, BCK/DSDL, LRCK/DSDBCK (in master mode), OVFR, OVFL
(5) Single rate, f
S
= 48 kHz
(6) Dual rate, f
S
= 96 kHz
(7) Quad rate, f
S
= 192 kHz
6 Submit Documentation Feedback Copyright © 2001 – 2007, Texas Instruments Incorporated
Product Folder Link(s): PCM1804