Datasheet

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APPLICATION INFORMATION
BOARD DESIGN AND LAYOUT CONSIDERATIONS
V
CC
, V
DD
Pins
V
IN
Pins
V
REF
X, V
COM
X Inputs
DATA/DSDR, BCK/DSDL, and LRCK/DSDBCK Pins
System Clock
Reset Control
APPLICATION CIRCUIT FOR SINGLE-ENDED INPUT
PCM1804
SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007
The digital and analog power supply lines to the PCM1804 should be bypassed to the corresponding ground pins
with 0.1- μ F ceramic and 10- μ F tantalum capacitors placed as close to the pins as possible to maximize the
dynamic performance of the ADC. Although the PCM1804 has two power lines to maximize the potential of
dynamic performance, using one common power supply is recommended to avoid unexpected power-supply
trouble like latch-up or power-supply sequence.
Use of 0.01- μ F film capacitors between V
IN
L+ and V
IN
L – and between V
IN
R+ and V
IN
R – is strongly
recommended to remove higher-frequency noise from the delta-sigma input section.
Use 0.1- μ F ceramic and 10- μ F tantalum capacitors between V
REF
L, V
REF
R, and corresponding AGNDx, to ensure
low-source impedance at ADC references. Use 0.1- μ F tantalum capacitors between V
COM
L, V
COM
R and
corresponding AGNDx to ensure low source impedance of common voltage. These capacitors should be located
as close as possible to the V
REF
L, V
REF
R, V
COM
L, and V
COM
R pins to reduce dynamic errors on references and
common voltage. The dc voltage level of these pins is 2.5 V.
The DATA/DSDR, BCK/DSDL, and LRCK/DSDBCK pins in master mode have large load drive capability.
Locating the buffer near the PCM1804 and minimizing the load capacitance, minimizes the digital-analog
crosstalk and maximizes the dynamic performance of the ADC.
The quality of the system clock can influence dynamic performance, as the PCM1804 operates based on a
system clock. Therefore, it might be necessary to consider the system clock duty, jitter, and the time difference
between system clock transition and BCK/DSDL or LRCK/DSDBCK transition in slave mode.
If capacitors larger than 10 μ F are used on V
REF
L and V
REF
R, an external reset control with a delay time
corresponding to the V
REF
L and V
REF
R response is required. Also, it works as a power-down control.
An application diagram for a single-ended input circuit is shown in Figure 44 . The maximum signal input voltage
and differential gain of this circuit is designed as Vinmax = 8.28 Vpp, Ad = 0.3. Differential gain (Ad) is given by
R3/R1(R4/R2) in a circuit configured as a normal inverted-gain amplifier. Resistor R5(R6) in the feedback loop
gives low-impedance drive operation and noise filtering for the analog input of the PCM1804. The circuit
technique using R5(R6) is recommended.
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Product Folder Link(s): PCM1804