Datasheet

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+
C
1
+
C
3
+
C
5
+
−
L-Channel In
Format [1:0]
Master/Slave
Oversampling
Ratio [2:0]
HPF Bypass
3.3 V
C
2
C
4
+
+
+
C
6
5 V
Control
+
−
R-Channel In
Overflow
Reset
System Clock
Data Clock
L-Channel Data Out
Audio Data
Processor
PCM1804
R-Channel Data Out
S0058-02
V
REF
L
AGNDL
V
COM
L
V
IN
L+
V
IN
L−
FMT0
FMT1
S/M
OSR0
OSR1
OSR2
BYPAS
DGND
V
DD
V
REF
R
AGNDR
V
COM
R
V
IN
R+
V
IN
R−
AGND
V
CC
OVFL
OVFR
RST
SCKI
LRCK/DSDBCK
BCK/DSDL
DATA/DSDR
PCM1804
SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007
Figure 43 illustrates a typical circuit connection diagram in the DSD data format operation.
A. C1, C2, C5, and C6: Bypass capacitors, 0.1- μ F ceramic and 10- μ F tantalum, depending on layout and power supply
B. C3 and C4: Bypass capacitors, 0.1- μ F tantalum, depending on layout and power supply
Figure 43. Typical Circuit Connection Diagram for DSD
28 Submit Documentation Feedback Copyright © 2001 – 2007, Texas Instruments Incorporated
Product Folder Link(s): PCM1804