Datasheet

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BCK
LRCK
DATA
t
w(BCKH)
t
w(BCKL)
t
(LRHD)
t
(LRCP)
t
(LRSU)
t
(BCKP)
t
(CKDO)
t
(LRDO)
1.4 V
1.4 V
0.5 V
DD
T0017-03
INTERFACE TIMING FOR DSD
D
n−3
D
n−2
D
n−1
D
n
D
n+1
D
n+2
D
n+3
D
n−3
D
n−2
D
n−1
D
n
D
n+1
D
n+2
D
n+3
DSDBCK
DSDL
DSDR
T0052−01
PCM1804
SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007
PARAMETERS MIN TYP MAX UNIT
t
(BCKP)
BCK period 1/(64 f
S
) 1/(48 f
S
)
t
w(BCKH)
BCK pulse duration, HIGH 32 ns
t
w(BCKL)
BCK pulse duration, LOW 32 ns
t
(LRSU)
LRCK setup time to BCK rising edge 12 ns
t
(LRHD)
LRCK hold time to BCK rising edge 12 ns
t
(LRCP)
LRCK period 1/f
S
t
(CKDO)
Delay time, BCK falling edge to DATA valid 5 25 ns
t
(LRDO)
Delay time, LRCK edge to DATA valid 5 25 ns
t
r
Rising time of all signals
(1)(2)
10 ns
t
f
Falling time of all signals
(1)(2)
10 ns
(1) Rising and falling times are measured from 10% to 90% of IN/OUT signals swing.
(2) Load capacitance of DATA/DSDR signal is 10 pF.
Figure 38. Audio Data Interface Timing for PCM (Slave Mode: LRCK and BCK Work as Inputs)
Figure 39 and Figure 40 illustrate the interface timing for DSD.
Figure 39. Audio Data Format
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