Datasheet

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BCK
LRCK
DATA
t
w(BCKH)
t
w(BCKL)
t
(CKLR)
t
(LRCP)
t
(BCKP)
t
(CKDO)
t
(LRDO)
0.5 V
DD
0.5 V
DD
0.5 V
DD
T0018-03
PCM1804
SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007
PARAMETERS MIN TYP MAX UNIT
t
(BCKP)
BCK period 1/(64 f
S
)
(3)
t
w(BCKH)
BCK pulse duration, HIGH 32 ns
t
w(BCKL)
BCK pulse duration, LOW 32 ns
t
(CKLR)
Delay time, BCK falling edge to LRCK valid – 5 15 ns
t
(LRCP)
LRCK period 1/f
S
t
(CKDO)
Delay time, BCK falling edge to DATA valid – 5 15 ns
t
(LRDO)
Delay time, LRCK edge to DATA valid – 5 15 ns
t
r
Rising time of all signals
(1)(2)
10 ns
t
f
Falling time of all signals
(1)(2)
10 ns
(1) Rising and falling times are measured from 10% to 90% of IN/OUT signal swing.
(2) Load capacitance of all signals is 10 pF.
(3) t
(BCKP)
is fixed at 1/(64 f
S
) in case of master mode.
Figure 37. Audio Data Interface Timing for PCM (Master Mode: LRCK and BCK Work as Outputs)
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