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1024 System Clock + 1/f
S
(Max)
Reset Reset Removal
4.4 V / 2.2 V
4 V / 2 V
3.6 V / 1.8 V
V
CC
, V
DD
Internal Reset
System Clock
T0014-07
t
(RST)
Reset Removal
1/f
S
(Max)
RST
Internal Reset
System Clock
RST Pulse Duration (t
(RST)
) = 40 ns (Min)
Reset
T0015-05
Ready / Operation
Power ON
RST ON
Reset Removal
Reset
1116/f
S
Zero Data
Converted Data
(2)
Internal Reset
Data
(1)
T0051-01
PCM1804
SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007
Figure 33. Internal Power-On-Reset Timing
Figure 34. External Reset Timing
(1) In the DSD mode, DSDL is also controlled like DSDR.
(2) The HPF transient response appears initially.
Figure 35. ADC Digital Output for Power-On Reset and RST Control
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Product Folder Link(s): PCM1804