Datasheet

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PIN ASSIGNMENTS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
REF
L
AGNDL
V
COM
L
V
IN
L+
V
IN
L−
FMT0
FMT1
S/M
OSR0
OSR1
OSR2
BYPAS
DGND
V
DD
V
REF
R
AGNDR
V
COM
R
V
IN
R+
V
IN
R−
AGND
V
CC
OVFL
OVFR
RST
SCKI
LRCK/DSDBCK
BCK/DSDL
DATA/DSDR
PCM1804 PACKAGE
(TOP VIEW)
P0007-02
PCM1804
SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields.
These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to
MIL-STD-883C, Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than
maximum-rated voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together
or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriate logic
voltage level, preferably either V
CC
or ground. Specific guidelines for handling devices of this type are contained in the publication
Electrostatic Discharge (ESD) (SSYA008 ), available from Texas Instruments.
2 Submit Documentation Feedback Copyright © 2001 – 2007, Texas Instruments Incorporated
Product Folder Link(s): PCM1804