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FEATURES APPLICATIONS

DESCRIPTION

PCM1804

SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007

FULL DIFFERENTIAL ANALOG INPUT 24-BIT, 192-kHz

STEREO A/D CONVERTER

• AV Amplifier

• 24-Bit Delta-Sigma Stereo A/D Converter

• MD Player

• High Performance:

• Digital VTR

– Dynamic Range: 112 dB (Typical)

• Digital Mixer

– SNR: 111 dB (Typical)

• Digital Recorder

– THD+N: – 102 dB (Typical)

• High-Performance Linear Phase Antialias

Digital Filter:

The PCM1804 is a high-performance, single-chip

– Pass-Band Ripple: ± 0.005 dB

stereo A/D converter with fully differential analog

– Stop-Band Attenuation: – 100 dB

voltage input. The PCM1804 uses a precision

delta-sigma modulator and includes a linear phase

• Fully Differential Analog Input: ± 2.5 V

antialias digital filter and high-pass filter (HPF) that

• Audio Interface: Master- or Slave-Mode

removes dc offset from the input signal. The

Selectable

PCM1804 is suitable for a wide variety of mid- to

• Data Formats: Left-Justified, I

S, Standard

high-grade consumer and professional applications,

24-Bit, and DSD

where excellent performance and 5-V analog supply

and 3.3-V digital power-supply operation are required.

• Function:

The PCM1804 can achieve both PCM audio and

– Peak Detection

DSD format due to the precision delta-sigma

– High-Pass Filter (HPF): – 3 dB at 1 Hz,

modulator. The PCM1804 is fabricated using an

= 48 kHz

advanced CMOS process and is available in a small

28-pin SSOP package.

• Sampling Rate up to 192 kHz

• System Clock: 128 f

, 256 f

, 384 f

512 f

, or 768 f

• Dual Power Supplies:

– 5 V for Analog

– 3.3 V for Digital

• Power Dissipation: 225 mW

• Small 28-Pin SSOP

• DSD Output: 1 Bit, 64 f

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2 System Two, Audio Precision are trademarks of Audio Precision, Inc.

3 All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (35 pages)

PAGE 1
PCM1804 SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007 FULL DIFFERENTIAL ANALOG INPUT 24-BIT, 192-kHz STEREO A/D CONVERTER FEATURES APPLICATIONS • 24-Bit Delta-Sigma Stereo A/D Converter • High Performance: – Dynamic Range: 112 dB (Typical) – SNR: 111 dB (Typical) – THD+N: –102 dB (Typical) • High-Performance Linear Phase Antialias Digital Filter: – Pass-Band Ripple: ±0.005 dB – Stop-Band Attenuation: –100 dB • Fully Differential Analog Input: ±2.
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PCM1804 www.ti.com SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007 This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C, Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated voltages to these high-impedance circuits.
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PCM1804 www.ti.
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PCM1804 www.ti.com SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007 Terminal Functions TERMINAL I/O DESCRIPTIONS NAME PIN AGND 23 – Analog ground AGNDL 2 – Analog ground for VREFL AGNDR 27 – Analog ground for VREFR BCK/DSDL 16 I/O Bit clock input/output in PCM mode. L-channel audio data output in DSD mode. (1) (1) BYPAS 12 I HPF bypass control. High: HPF disabled, Low: HPF enabled DATA/DSDR 15 O L-channel and R-channel audio data output in PCM mode.
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PCM1804 www.ti.com SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) Supply voltage VCC –0.3 V to 6.5 V VDD –0.3 V to 4 V Ground voltage differences AGND, AGNDL, AGNDR, DGND Supply voltage difference VCC, VDD Digital input voltage Analog input voltage ±0.1 V VCC – VDD < 3 V FMT0, FMT1, S/M, OSR0, OSR1, OSR2, SCKI, RST –0.3 V to 6.5 V BYPAS, DATA/DSDR, BCK/DSDL, LRCK/DSDBCK, OVFL, OVFR –0.
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PCM1804 www.ti.com SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007 ELECTRICAL CHARACTERISTICS All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, single-speed mode, fS = 48 kHz, system clock = 256 fS, 24-bit data, unless otherwise noted.
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PCM1804 www.ti.com SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, single-speed mode, fS = 48 kHz, system clock = 256 fS, 24-bit data, unless otherwise noted. PARAMETER DYNAMIC PERFORMANCE TEST CONDITIONS TYP MAX –102 –95 UNIT (8) VIN = –0.5 dB VIN = –60 dB VIN = –0.5 dB THD+N PCM1804DB MIN Total harmonic distortion plus noise VIN = –60 dB VIN = –0.
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PCM1804 www.ti.com SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, single-speed mode, fS = 48 kHz, system clock = 256 fS, 24-bit data, unless otherwise noted. PARAMETER TEST CONDITIONS PCM1804DB MIN TYP MAX 4.75 5 5.25 3 3.3 3.6 (9) (10) (11) 35 45 VDD = 3.3 V (9) (12) 15 20 VDD = 3.3 V (10) (12) 27 VDD = 3.
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PCM1804 www.ti.com SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007 TYPICAL PERFORMANCE CURVES - SINGLE RATE All specifications at TA = 25°C, VCC = 3.3 V, VDD = 5 V, master mode, fS = 48 kHz, system clock = 256 fS, 24-bit data, unless otherwise noted. DYNAMIC RANGE AND SNR vs TEMPERATURE −35 −95 −40 −100 −45 −0.
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PCM1804 www.ti.com SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007 TYPICAL PERFORMANCE CURVES - SINGLE RATE (continued) All specifications at TA = 25°C, VCC = 3.3 V, VDD = 5 V, master mode, fS = 48 kHz, system clock = 256 fS, 24-bit data, unless otherwise noted. DYNAMIC RANGE AND SNR vs SAMPLING FREQUENCY −35 −95 −40 −100 −45 −0.5 dB −105 −50 −60 dB −110 −55 32 44.
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PCM1804 www.ti.com SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007 TYPICAL PERFORMANCE CURVES - SINGLE RATE (continued) All specifications at TA = 25°C, VCC = 3.3 V, VDD = 5 V, master mode, fS = 48 kHz, system clock = 256 fS, 24-bit data, unless otherwise noted. AMPLITUDE vs FREQUENCY AMPLITUDE vs FREQUENCY 0 0 Output Spectrum: −0.
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PCM1804 www.ti.com SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007 TYPICAL PERFORMANCE CURVES - QUAD RATE All specifications at TA = 25°C, VCC = 3.3 V, VDD = 5 V, master mode, 24-bit data, unless otherwise noted. AMPLITUDE vs FREQUENCY AMPLITUDE vs FREQUENCY 0 0 fS = 192 kHz, System Clock = 128 fS −20 −40 −40 Output Spectrum: −0.
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PCM1804 www.ti.com SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER LINEAR PHASE ANTIALIAS DIGITAL FILTER FREQUENCY RESPONSE - Single-Rate OVERALL CHARACTERISTICS FOR SINGLE-RATE FILTER STOP-BAND ATTENUATION CHARACTERISTICS FOR SINGLE-RATE FILTER 50 0 −10 fS = 48 kHz fS = 48 kHz −20 0 −30 Amplitude − dB Amplitude − dB −40 −50 −100 −50 −60 −70 −80 −90 −100 −110 −150 −120 −130 −140 −200 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.
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PCM1804 www.ti.com SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER (continued) LINEAR PHASE ANTIALIAS DIGITAL FILTER FREQUENCY RESPONSE - Dual-Rate OVERALL CHARACTERISTICS FOR DUAL-RATE FILTER STOP-BAND ATTENUATION CHARACTERISTICS FOR DUAL-RATE FILTER 50 0 fS = 96 kHz −10 fS = 96 kHz −20 0 −30 Amplitude − dB Amplitude − dB −40 −50 −100 −50 −60 −70 −80 −90 −100 −110 −150 −120 −130 −140 −200 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.
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PCM1804 www.ti.com SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER (continued) LINEAR PHASE ANTIALIAS DIGITAL FILTER FREQUENCY RESPONSE - Quad-Rate OVERALL CHARACTERISTICS FOR QUAD-RATE FILTER STOP-BAND ATTENUATION CHARACTERISTICS FOR QUAD-RATE FILTER 50 0 fS = 192 kHz −10 fS = 192 kHz −20 0 −30 Amplitude − dB Amplitude − dB −40 −50 −100 −50 −60 −70 −80 −90 −100 −110 −150 −120 −130 −140 −200 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.
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PCM1804 www.ti.com SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER (continued) HIGH-PASS FILTER (HPF) FREQUENCY RESPONSE STOP-BAND CHARACTERISTICS PASS-BAND CHARACTERISTICS 0.2 0 −10 0.0 −20 Amplitude − dB Amplitude − dB −30 −40 −50 −60 −70 −80 −0.2 −0.4 −0.6 −0.8 −90 −100 0.0 0.1 0.2 0.3 0.4 Normalized Frequency − y fS/1000 −1.0 0.0 G028 0.5 1.0 1.5 2.0 2.5 3.0 Normalized Frequency − y fS/1000 Figure 28. 3.5 4.0 G029 Figure 29.
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PCM1804 www.ti.com SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007 PRINCIPLES OF OPERATION (continued) OSR0 CLK Control SCKI OSR1 OSR2 VINL+ VINL− Delta-Sigma Modulator (L) Decimation Filter (L) HPF S/M FMT0 VCOML AGNDL VREFL VREFR AGNDR FMT1 VREFL Serial Output Interface VREFR LRCK/DSDBCK BCK/DSDL DATA/DSDR VCOMR VINR+ VINR− Decimation Filter (R) Delta-Sigma Modulator (R) OVFL HPF OVFR BYPAS Power Supply VCC AGND RST DGND VDD B0029-01 Figure 30.
PAGE 18
PCM1804 www.ti.com SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007 PRINCIPLES OF OPERATION (continued) SYSTEM CLOCK INPUT The PCM1804 supports 128 fS, 192 fS (only in master mode at quad rate), 256 fS, 384 fS, 512 fS, and 768 fS as a system clock, where fS is the audio sampling frequency. The system clock must be supplied on SCKI (pin 18). Table 3 shows the relationship of typical sampling frequency and the system clock frequency, and Figure 32 shows system clock timing.
PAGE 19
PCM1804 www.ti.com SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007 Table 1.
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PCM1804 www.ti.com SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007 VCC, VDD 4.4 V / 2.2 V 4V/2V 3.6 V / 1.8 V Reset Reset Removal Internal Reset 1024 System Clock + 1/fS (Max) System Clock T0014-07 Figure 33. Internal Power-On-Reset Timing RST t(RST) RST Pulse Duration (t(RST)) = 40 ns (Min) Reset Reset Removal Internal Reset 1/fS (Max) System Clock T0015-05 Figure 34.
PAGE 21
PCM1804 www.ti.com SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007 AUDIO DATA INTERFACE The PCM1804 interfaces the audio system through BCK/DSDL (pin 16), LRCK/DSDBCK (pin 17), and DATA/DSDR (pin 15). The PCM1804 needs RST = low when in the interface mode and/or the data format are changed. INTERFACE MODE The PCM1804 supports master mode and slave mode as interface modes, which are selected by S/M (pin 8) as shown in Table 4.
PAGE 22
PCM1804 www.ti.com SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007 INTERFACE TIMING FOR PCM Figure 36 through Figure 38 illustrate the interface timing for PCM.
PAGE 23
PCM1804 www.ti.com SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007 t(LRCP) 0.5 VDD LRCK tw(BCKL) t(CKLR) tw(BCKH) 0.5 VDD BCK t(CKDO) t(BCKP) t(LRDO) 0.
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PCM1804 www.ti.com SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007 t(LRCP) 1.4 V LRCK tw(BCKL) tw(BCKH) t(LRSU) t(LRHD) 1.4 V BCK t(CKDO) t(BCKP) t(LRDO) 0.
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PCM1804 www.ti.com SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007 tw(BCKH) tw(BCKL) t(CKDO) DSDBCK 0.5 VDD t(BCKP) DSDL DSDR 0.
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PCM1804 www.ti.com SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007 OVERFLOW FLAG FOR PCM The PCM1804 has two overflow flag pins, OVFR (pin 20) and OVFL (pin 21). The pins go to high as soon as the analog input goes across the full-scale range. The high level is held for 1.016 s at maximum, and returns to low if the analog input does not go across the full-scale range for the period.
PAGE 27
PCM1804 www.ti.com SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007 TYPICAL CIRCUIT CONNECTION DIAGRAM Figure 42 illustrates a typical circuit connection diagram in the PCM data format operation. PCM1804 C1 + 1 VREFL VREFR 2 C3 AGNDL AGNDR VCOML VCOMR VINL+ VINR+ VINL− VINR− FMT0 AGND FMT1 VCC + 3 4 + L-Channel In 5 − 6 Format [1:0] 8 9 Control 10 Oversampling Ratio [2:0] 11 12 13 3.
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PCM1804 www.ti.com SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007 Figure 43 illustrates a typical circuit connection diagram in the DSD data format operation. PCM1804 C1 + 1 VREFL VREFR 2 AGNDL C3 AGNDR + 3 VCOML VCOMR VINL+ VINR+ VINL− VINR− FMT0 AGND FMT1 VCC 4 + L-Channel In 5 − 6 Format [1:0] 8 9 Control 10 Oversampling Ratio [2:0] 11 12 HPF Bypass 13 3.
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PCM1804 www.ti.com SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007 APPLICATION INFORMATION BOARD DESIGN AND LAYOUT CONSIDERATIONS VCC, VDD Pins The digital and analog power supply lines to the PCM1804 should be bypassed to the corresponding ground pins with 0.1-μF ceramic and 10-μF tantalum capacitors placed as close to the pins as possible to maximize the dynamic performance of the ADC.
PAGE 30
PCM1804 www.ti.com SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007 R3 = 1 kΩ C(1) 4.7 kΩ 4.7 kΩ Analog In _ 10 µF + + PCM1804 R1 = 3.3 kΩ R5 = 47 Ω _ VIN− + OPA2134 1/2 OPA2134 1/2 VCOM 0.01 µF R4 = 1 kΩ 0.1 µF C(1) 10 µF R2 = 3.3 kΩ R6 = 47 Ω _ + + VIN+ OPA2134 1/2 S0059-01 (1) A capacitor value of 1800 pF is recommended, unless an input signal greater than –6 dBFS at 100 kHz or higher is applied in the DSD mode. In that case, 3300 pF is recommended. Figure 44.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Nov-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device PCM1804DBR Package Package Pins Type Drawing SSOP DB 28 SPQ Reel Reel Diameter Width (mm) W1 (mm) 2000 330.0 17.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 8.5 10.8 2.4 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Nov-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PCM1804DBR SSOP DB 28 2000 336.6 336.6 28.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.