Datasheet

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RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS
PCM1803A
SLES142A – JUNE 2005 – REVISED AUGUST 2006
over operating free-air temperature range
MIN NOM MAX UNIT
Analog supply voltage, V
CC
4.5 5 5.5 V
Digital supply voltage, V
DD
2.7 3.3 3.6 V
Analog input voltage, full-scale (–0 dB) 3 Vp-p
Digital input logic family TTL
System clock 8.192 49.152 MHz
Digital input clock frequency
Sampling clock 32 96 kHz
Digital output load capacitance 20 pF
Operating free-air temperature, T
A
–25 85 °C
All specifications at T
A
= 25°C, V
CC
= 5 V, V
DD
= 3.3 V, master mode, f
S
= 44.1 kHz, system clock = 384 f
S
,
oversampling ratio = ×128, 24-bit data (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 24 Bits
DATA FORMAT
Audio data interface format Left-justified, I
2
S, right-justified
Audio data bit length 20, 24 Bits
Audio data format MSB-first, 2s complement
f
S
Sampling frequency 16 44.1 96 kHz
256 f
S
4.096 11.2896 24.576
384 f
S
6.144 16.9344 36.864
System clock frequency MHz
512 f
S
8.192 22.5792 49.152
768 f
S
12.288 33.8688 –
INPUT LOGIC
V
IH
(1)
2 V
DD
V
IL
(1)
0 0.8
Input logic-level voltage Vdc
V
IH
(2) (3)
2 5.5
V
IL
(2) (3)
0 0.8
I
IH
(1) (2)
V
IN
= V
DD
± 10
I
IL
(1) (2)
V
IN
= 0 ± 10
Input logic-level current µ A
I
IH
(3)
V
IN
= V
DD
65 100
I
IL
(3)
V
IN
= 0 ± 10
OUTPUT LOGIC
V
OH
(4)
I
OUT
= –4 mA 2.8
Output logic-level voltage Vdc
V
OL
(4)
I
OUT
= 4 mA 0.5
DC ACCURACY
Gain mismatch, channel-to-channel ± 1 ± 3 % of FSR
Gain error ± 2 ± 4 % of FSR
Bipolar zero error HPF bypass ± 0.4 % of FSR
(1) Pins 10–11: LRCK, BCK (Schmitt-trigger input, in slave mode)
(2) Pin 15: SCKI (Schmitt-trigger input, 5-V tolerant)
(3) Pins 7–9, 16–20: PDWN, BYPAS, TEST, OSR, FMT0, FMT1, MODE0, MODE1 (Schmitt-trigger input, with 50-k Ω typical pulldown
resistor, 5-V tolerant)
(4) Pins 10–12: LRCK, BCK (in master mode), DOUT
4
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