Datasheet

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BOARD DESIGN and LAYOUT CONSIDERATIONS
V
CC
, V
DD
Pins
AGND, DGND Pins
V
IN
L, V
IN
R Pins
V
REF
1 Pin
V
REF
2 Pin
DOUT Pin
System Clock
PCM1803A
SLES142A – JUNE 2005 – REVISED AUGUST 2006
APPLICATION INFORMATION (continued)
The digital and analog power-supply lines to the PCM1803A should be bypassed to the corresponding ground
pins with 0.1- µ F ceramic and 10- µ F electrolytic capacitors, as close to the pins as possible, to maximize the
dynamic performance of the ADC.
To maximize the dynamic performance of the PCM1803A, the analog and digital grounds are not connected
internally. These grounds should have low impedance to avoid digital noise feeding back into the analog ground.
Therefore, they should be connected directly to each other under the part to reduce potential noise problems.
The V
IN
L and V
IN
R pins need a simple external RC filter (f
C
= 160 kHz) as an antialiasing filter to remove
out-of-band noise from the audio band. If the input signal includes noise with a frequency near the oversampling
frequency (64 f
S
or 128 f
S
), the noise is folded into the baseband (audio band) signal through A-to-D conversion.
The recommended R value is 100 Ω . Film-type capacitors of 0.01- µ F should be located as close as possible to
the V
IN
L and V
IN
R pins and should be terminated to GND as close as possible to the AGND pin to maximize the
dynamic performance of ADC, by suppressing kickback noise from the PCM1803A.
A 0.1- µ F ceramic capacitor and 10- µ F electrolytic capacitor are recommended between V
REF
1 and AGND to
ensure low source impedance of the ADC references. These capacitors should be located as close as possible
to the V
REF
1 pin to reduce dynamic errors on the ADC reference.
The differential voltage between V
REF
2 and AGND sets the analog input full-scale range. A 0.1- µ F ceramic
capacitor and 10- µ F electrolytic capacitor are recommended between V
REF
2 and AGND. These capacitors
should be located as close as possible to the V
REF
2 pin to reduce dynamic errors on the ADC reference.
The DOUT pin has enough load drive capability, but if the DOUT line is long, locating a buffer near the
PCM1803A and minimizing load capacitance is recommended to minimize the digital-analog crosstalk and
maximize the dynamic performance of the ADC.
The quality of the system clock can influence the dynamic performance, because the PCM1803A operates
based on a system clock. Therefore, it may be required to consider the system-clock duty, jitter, and the time
difference between system-clock transition and BCK or LRCK transition in the slave mode.
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