Datasheet

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APPLICATION INFORMATION
TYPICAL CIRCUIT CONNECTION DIAGRAM
V
IN
L
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
PCM1803A
V
IN
R
V
REF
1
V
REF
2
V
CC
AGND
PDWN
BYPAS
TEST
LRCK
MODE1
DGND
MODE0
FMT1
FMT0
OSR
DOUT
BCK
V
DD
SCKI
+
Oversampling
System Clock
L-Ch IN
R-Ch IN
+5 V
C
4
+
C
5
Power Down
LCF Bypass
Control
+
C
3
L/R Clock
Audio Data
Processor
Mode [1:0]
Format [1:0]
+3.3 V
Data Clock
Data Out
+
C
1
+
C
2
Control
R
1
S0026-03
+
C
6
R
2
C
7
C
8
PCM1803A
SLES142A – JUNE 2005 – REVISED AUGUST 2006
Figure 24 illustrates a typical circuit connection diagram where the cutoff frequency of the input HPF is about
160 kHz.
NOTES:
A. C
1
, C
2
: A 1- µ F electrolytic capacitor gives a 4-Hz ( τ = 1 µ F × 40 k Ω ) cutoff frequency for the input HPF in normal
operation and requires a power-on settling time with a 40-ms time constant during the power-on initialization period.
B. C
3
, C
4
: Bypass capacitors are 0.1- µ F ceramic and 10- µ F electrolytic, depending on layout and power supply.
C. C
5
, C
6
: Recommended capacitors are 0.1- µ F ceramic and 10- µ F electrolytic.
D. C
7
, C
8
, R
1
, R
2
: A 0.01- µ F film-type capacitor and 100- Ω resistor give a 160-kHz ( τ = 0.01 µ F × 100 Ω ) cutoff
frequency for the anti-aliasing filter in normal operation.
Figure 24. Typical Application Diagram
18
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