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SYNCHRONIZATION WITH DIGITAL AUDIO SYSTEM
1/f
S
32/f
S
NORMAL DATAZERO DATA
UNDEFINED
DATA
NORMAL DATA
SYNCHRONOUSASYNCHRONOUSSYNCHRONOUS
Resynchronization
Synchronization Lost
DOUT
State of Synchronization
T0020-05
PCM1803A
SLES142A – JUNE 2005 – REVISED AUGUST 2006
In slave mode, the PCM1803A operates under LRCK, synchronized with system clock SCKI. The PCM1803A
does not need a specific phase relationship between LRCK and SCKI, but does require the synchronization of
LRCK and SCKI.
If the relationship between LRCK and SCKI changes more than ± 6 BCKs for 64 BCK/frame ( ± 5 BCKs for 48
BCK/frame) during one sample period due to LRCK or SCKI jitter, internal operation of the ADC halts within 1/f
S
,
and digital output is forced to zero data (BPZ code) until resynchronization between LRCK and SCKI occurs.
In case of changes less than ± 5 BCKs for 64 BCK/frame ( ± 4 BCKs for 48 BCK/frame), resynchronization does
not occur and the previously explained digital output control and discontinuity do not occur.
Figure 23 illustrates the digital output response for loss of synchronization and resynchronization. During
undefined data, the PCM1803A can generate some noise in the audio signal. Also, the transition of normal to
undefined data and undefined or zero data to normal creates a discontinuity in the data of the digital output,
which can generate some noise in the audio signal.
Figure 23. ADC Digital Output for Loss of Synchronization and Resynchronization
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