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BCK
LRCK
DOUT
t
(BCKH)
t
(BCKL)
t
(CKLR)
t
(LRCP)
t
(BCKP)
t
(CKDO)
t
(LRDO)
0.5 V
DD
0.5 V
DD
0.5 V
DD
T0018-02
BCK
SCKI
t
(SCKBCK)
1.4 V
0.5 V
DD
T0074-01
t
(SCKBCK)
PCM1803A
SLES142A – JUNE 2005 – REVISED AUGUST 2006
SYMBOL PARAMETER MIN TYP MAX UNIT
t
(BCKP)
BCK period 150 1/(64 f
S
) 1000 ns
t
(BCKH)
BCK pulse duration, HIGH 65 600 ns
t
(BCKL)
BCK pulse duration, LOW 65 600 ns
t
(CKLR)
Delay time, BCK falling edge to LRCK valid –10 20 ns
t
(LRCP)
LRCK period 10 1/f
S
65 µ s
t
(CKDO)
Delay time, BCK falling edge to DOUT valid –10 20 ns
t
(LRDO)
Delay time, LRCK edge to DOUT valid –10 20 ns
t
r
Rising time of all signals 20 ns
t
f
Falling time of all signals 20 ns
NOTE: Timing measurement reference level is 1.4 V for input and 0.5 V
DD
for output. Rising and falling time is measured
from 10% to 90% of IN/OUT signal swing. Load capacitance of all signals is 20 pF.
Figure 21. Audio Data Interface Timing (Master Mode: LRCK and BCK Work as Outputs)
SYMBOL PARAMETER MIN TYP MAX UNIT
t
(SCKBCK)
Delay time, SCKI rising edge to BCK edge 5 30 ns
NOTE: Timing measurement reference level is 1.4 V for input and 0.5 V
DD
for output. Load capacitance of BCK is 20 pF.
Figure 22. Audio Clock Interface Timing (Master Mode: BCK Works as Output)
15
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