Datasheet

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Board Design and Layout Considerations
V
CC
, V
DD
Pins
AGND, DGND Pins
V
IN
Pins
V
REF
1 Pin
V
REF
2 Pin
DOUT Pin
System Clock
PCM1802
SLES023C – DECEMBER 2001 – REVISED JANUARY 2005
APPLICATION INFORMATION (continued)
The digital and analog power supply lines to the PCM1802 should be bypassed to the corresponding ground pins
with 0.1- µ F ceramic and 10- µ F tantalum capacitors as close to the pins as possible to maximize the dynamic
performance of the ADC.
To maximize the dynamic performance of the PCM1802, the analog and digital grounds are not connected
internally. These grounds should have low impedance to avoid digital noise feeding back into the analog ground.
They should be connected directly to each other under the parts to reduce the potential noise problem.
A 1- µ F capacitor is recommended as an ac-coupling capacitor, which gives an 8-Hz cutoff frequency. If a higher
full-scale input voltage is required, it can be accommodated by adding only one series resistor to each V
IN
pin.
A ceramic capacitor of 0.1 µ F and an electrolytic capacitor of 10 µ F are recommended between V
REF
1 and
AGND to ensure low source impedance for the ADC references. These capacitors should be located as close as
possible to the V
REF
1 pin to reduce dynamic errors on the ADC references.
The differential voltage between V
REF
2 and AGND sets the analog input full-scale range. A ceramic capacitor of
0.1 µ F and an electrolytic capacitor of 10 µ F are recommended between V
REF
2 and AGND with the insertion of a
1-k Ω resistor between V
CC
and V
REF
2 when using a noisy analog power supply. These capacitors and resistor
are not required for a clean analog supply. These capacitors should be located as close as possible to the V
REF
2
pin to reduce dynamic errors on the ADC references. Full-scale input level is affected by this 1-k Ω resistor,
decreasing by 3%.
The DOUT pin has enough load drive capability, but locating a buffer near the PCM1802 and minimizing load
capacitance is recommended if the DOUT line is long, in order to minimize the digital-analog crosstalk and
maximize the dynamic performance of the ADC.
The quality of the system clock can influence dynamic performance, as the PCM1802 operates based on the
system clock. In slave mode, it may be necessary to consider the system-clock duty cycle, jitter, and the time
difference between the system clock transition and the BCK or LRCK transition.
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