Datasheet

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Interface Mode

Master mode

Slave mode

Data Format

PCM1802

SLES023C – DECEMBER 2001 – REVISED JANUARY 2005

The PCM1802 supports master mode and slave mode as interface modes, and they are selected by MODE1

(pin 20) and MODE0 (pin 19) as shown in Table 2 .

In master mode, the PCM1802 provides the timing for serial audio data communications between the PCM1802

and the digital audio processor or external circuit. In slave mode, the PCM1802 receives the timing for data

transfer from an external controller.

Table 2. Interface Mode

MODE1 MODE0 INTERFACE MODE

0 0 Slave mode (256 f

, 384 f

, 512 f

, 768 f

)

0 1 Master mode (512 f

)

1 0 Master mode (384 f

)

1 1 Master mode (256 f

)

In master mode, BCK, LRCK, and FSYNC work as output pins, and these pins are controlled by timing which is

generated in the clock circuit of the PCM1802. FSYNC is used to designate the valid data from the PCM1802.

The rising edge of FSYNC indicates the starting point of the converted audio data and the falling edge of this

signal indicates the ending point of the data. The frequency of this signal is fixed at 2 × LRCK. The duty cycle

ratio depends on data bit length. The frequency of BCK is fixed at 64 × LRCK. The 768 f

system clock is not

available in master mode.

In slave mode, BCK, LRCK, and FSYNC work as input pins. FSYNC is used to enable the BCK signal, and the

PCM1802 can shift out the converted data while FSYNC is HIGH. The PCM1802 accepts either the

64 BCK/LRCK or the 48 BCK/LRCK format. The delay of FSYNC from the LRCK transition must be within

16 BCKs for the 64 BCK/LRCK format and within 12 BCKs for the 48 BCK/LRCK format.

The PCM1802 supports four audio data formats in both master and slave modes, and they are selected by FMT1

(pin 18) and FMT0 (pin 17) as shown in Table 3 . Figure 24 and Figure 26 illustrate the data formats in slave

mode and master mode, respectively.

Table 3. Data Format

FORMAT# FMT1 FMT0 FORMAT

0 0 0 Left-justified, 24-bit

1 0 1 I

S, 24-bit

2 1 0 Right-justified, 24-bit

3 1 1 Right-justified, 20-bit