Datasheet

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Power-On Reset Sequence
System Clock
2.6 V
2.2 V
1.8 V
Internal Reset
DOUT
Zero Data Normal Data
Reset
V
DD
Reset Removal
1024 System Clocks 4480 / f
S
T0014-05
Serial Audio Data Interface
PCM1802
SLES023C – DECEMBER 2001 – REVISED JANUARY 2005
The PCM1802 has an internal power-on reset circuit, and initialization (reset) is performed automatically when
the power supply (V
DD
) exceeds 2.2 V (typical). While V
DD
< 2.2 V (typical), and for 1024 system-clock counts
after V
DD
> 2.2 V (typical), the PCM1802 stays in the reset state and the digital output is forced to zero. The
digital output is valid after the reset state is released and the time of 4480/f
S
has passed. Figure 23 illustrates the
internal power-on reset timing and the digital output for power-on reset.
Figure 23. Internal Power-On Reset Timing
The PCM1802 interfaces with the audio system through BCK (pin 11), LRCK (pin 10), FSYNC (pin 9), and DOUT
(pin 12).
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