Datasheet

www.ti.com
System Clock
SCKI
0.8 V
SCKI
2 V
t
(SCKL)
t
(SCKH)
T0005A07
PCM1802
SLES023C – DECEMBER 2001 – REVISED JANUARY 2005
PRINCIPLES OF OPERATION (continued)
The PCM1802 supports 256 f
S
, 384 f
S
, 512 f
S
, and 768 f
S
as the system clock, where f
S
is the audio sampling
frequency. The system clock must be supplied on SCKI (pin 15).
The PCM1802 has a system clock detection circuit which automatically senses if the system clock is operating at
256 f
S
, 384 f
S
, 512 f
S
, or 768 f
S
in slave mode. In master mode, the system clock frequency must be selected by
MODE0 (pin 19) and MODE1 (pin 20), and 768 f
S
is not available. For system clock inputs of 384 f
S
, 512 f
S
, and
768 f
S
, the system clock is divided to 256 f
S
automatically, and the 256 f
S
clock is used to operate the
delta-sigma modulator and the digital filter.
Table 1 shows the relationship of typical sampling frequencies and system clock frequencies, and Figure 22
shows system clock timing.
Table 1. Sampling Frequency and System Clock Frequency
SAMPLING RATE SYSTEM CLOCK FREQUENCY (MHz)
FREQUENCY
256 f
S
384 f
S
512 f
S
768 f
S
(kHz)
32 8.192 12.288 16.384 24.576
44.1 11.2896 16.9344 22.5792 33.8688
48 12.288 18.432 24.576 36.864
64 16.384 24.576 32.768 49.152
88.2 22.5792 33.8688 45.1584 —
96 24.576 36.864 49.152 —
PARAMETER MIN MAX UNIT
t
(SCKH)
System clock-pulse duration, high 7 ns
t
(SCKL)
System clock-pulse duration, low 7 ns
Figure 22. System Clock Timing
13