Datasheet

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PRINCIPLES OF OPERATION
Single-End
/Differential
Converter
BCK
V
IN
L
Reference
Single-End
/Differential
Converter
V
REF
1
V
REF
2
V
IN
R
5
th
Order
Delta-Sigma
Modulator
5
th
Order
Delta-Sigma
Modulator
×1/64 (×1/128)
Decimation
Filter
with
High-Pass Filter
Power Supply
AGNDV
CC
V
DD
DGND
Clock and Timing Control
Serial
Interface
Mode/
Format
Control
LRCK
FSYNC
DOUT
FMT0
FMT1
MODE0
MODE1
BYPAS
OSR
PDWN
SCKI
B0004-07
PCM1802
SLES023C – DECEMBER 2001 – REVISED JANUARY 2005
The PCM1802 consists of a reference circuit, two channels of single-ended-to-differential converter, a fifth-order
delta-sigma modulator with full differential architecture, a decimation filter with high-pass filter, and a serial
interface circuit. Figure 19 illustrates the total architecture of the PCM1802, Figure 20 illustrates the architecture
of single-ended-to-differential converter and antialiasing filter, and Figure 21 is the block diagram of the fifth-order
delta-sigma modulator and transfer function. An on-chip high-precision reference with one external capacitor
provides all reference voltages that are needed in the PCM1802 and defines the full-scale voltage range for both
channels. On-chip single-ended-to-differential signal converters save the design, space, and extra parts cost for
external signal converters. Full-differential architecture provides a wide dynamic range and excellent
power-supply rejection performance. The input signal is sampled at a × 64 or × 128 oversampling rate, thus
eliminating an external sample-hold amplifier. A fifth-order delta-sigma noise shaper, which consists of five
integrators using the switched capacitor technique and a comparator, shapes the quantization noise generated
by the comparator and 1-bit DAC outside of the audio signal band. The high-order delta-sigma modulation
randomizes the modulator outputs and reduces the idle tone level. The 64-f
S
or 128-f
S
, 1-bit stream from the
delta-sigma modulator is converted to a 1-f
S
, 24-bit or 20-bit digital signal by removing high-frequency noise
components with a decimation filter. The dc component of the signal is removed by the HPF, and the HPF output
is converted to a time-multiplexed serial signal through the serial interface, which provides flexible serial formats.
Figure 19. Block Diagram
11