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INTERFACE TIMING
BCK
LRCK
DOUT
t
(BCKH)
t
(BCKL)
t
(LRHD)
t
(LRCP)
t
(LRSU)
t
(BCKP)
t
(CKDO)
t
(LRDO)
1.4 V
1.4 V
0.5 V
DD
T0017-02
SYNCHRONIZATION WITH DIGITAL AUDIO SYSTEM
PCM1801
SBAS131C – OCTOBER 2000 – REVISED JULY 2007
Figure 26 illustrates the interface timing.
DESCRIPTION SYMBOL MIN TYP MAX UNITS
BCK period t
(BCKP)
300 ns
BCK pulse duration, HIGH t
(BCKH)
120 ns
BCK pulse duration, LOW t
(BCKL)
120 ns
LRCK setup time to BCK rising edge t
(LRSU)
80 ns
LRCK hold time to BCK rising edge t
(LRHD)
40 ns
LRCK period t
(LRCP)
20 μ s
Delay time, BCK falling edge to DOUT valid t
(CKDO)
–20 40 ns
Delay time, LRCK edge to DOUT valid t
(LRDO)
–20 40 ns
Rising time of all signals t
(RISE)
20 ns
Falling time of all signals t
(FALL)
20 ns
NOTE: Timing measurement reference level is (V
IH
+ V
IL
)/2. Rising and falling time is
measured from 10% to 90% of the I/O signal swing. Load capacitance of the DOUT
signal is 20 pF.
Figure 26. Audio Data Interface Timing
The PCM1801 operates with LRCK synchronized to the system clock (SCKI). The PCM1801 does not require a
specific phase relationship between LRCK and SCKI, but does require the synchronization of LRCK and SCKI. If
the relationship between LRCK and SCKI changes more than 6 bit clocks (BCK) during one sample period due
to LRCK or SCKI jitter, internal operation of the ADC halts within 1/f
S
and the digital output is forced to BPZ until
resynchronization between LRCK and SCKI is completed. In case of changes less than 5 bit clocks (BCK),
resynchronization does not occur and the previously described digital output control and discontinuity do not
occur. Figure 27 illustrates the ADC digital output for lost synchronization and resynchronization. During
undefined data, some noise may be generated in the audio signal. Also, the transition of normal to undefined
data and undefined or zero data to normal makes a discontinuity of data on the digital output and may generate
some noise in the audio signal.
15
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