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SCKI
0.8 V
2 V
t
CLKIL
t
CLKIH
T0005-04
POWER-ON RESET
1024 System Clocks
Reset
Reset Removal
4.4 V
4 V
3.6 V
V
CC
/ V
DD
Internal Reset
System Clock
3 Clocks Minimum
DOUT
Zero Data Normal Data
(1)
18436 / f
S
T0014-02
PCM1801
SBAS131C – OCTOBER 2000 – REVISED JULY 2007
Table 2. System Clock Frequencies
SAMPLING RATE FREQUENCY SYSTEM CLOCK FREQUENCY
(kHz)
256 f
s
384 f
s
512 f
s
32 8.1920 12.2880 16.3840
44.1 11.2896 16.9344 22.5792
48 12.2880 18.4320 24.5760
System clock pulse duration, HIGH t
(CLKIH)
12 ns (min)
System clock pulse duration, LOW t
(CLKIL)
12 ns (min)
Figure 23. System Clock Timing
The PCM1801 has an internal power-on reset circuit, which initializes (resets) when the supply voltage
(V
CC
/V
DD
) exceeds 4 V (typical). Because the system clock is used as the clock signal for the reset circuit, the
system clock must be supplied as soon as power is applied; more specifically, the device must receive at least
three system clock cycles before V
DD
> 4 V. While V
CC
/V
DD
< 4 V (typical) and for 1024 system clock cycles after
V
CC
/V
DD
> 4 V, the PCM1801 stays in the reset state and the digital output is forced to zero. The digital output is
valid 18,436 f
S
periods after release from the reset state. Figure 24 illustrates the internal power-on reset timing
and the digital output for power-on reset.
(1) The transient response (exponentially attenuated signal from ± 0.2% dc of FSR with a 200-ms time constant) appears
initially.
Figure 24. Internal Power-On Reset Timing
13
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