Datasheet

APPLICATION INFORMATION
BOARD DESIGN AND LAYOUT CONSIDERATIONS
V
CC
, V
DD
PINS
AGND, DGND PINS
V
IN
PINS
V
REF
INPUTS
C
IN
P and C
IN
N INPUTS
DOUT, BCK, LRCK, FSYNC PINS
SYSTEM CLOCK
RSTB CONTROL
PCM1800
SBAS071B – OCTOBER 2000 – REVISED AUGUST 2008 ............................................................................................................................................... www.ti.com
The digital and analog power supply lines to the PCM1800 should be bypassed to the corresponding ground pins
with both 0.1- µ F ceramic and 10- µ F tantalum capacitors as close to the pins as possible to maximize the
dynamic performance of the ADC. Although the PCM1800 has two power lines to maximize the potential of
dynamic performance, using one common power supply is recommended to avoid unexpected power supply
problems, such as latch-up or power supply sequence.
To maximize the dynamic performance of the PCM1800, the analog and digital grounds are not internally
connected. These points should have low impedance to avoid digital noise feedback into the analog ground.
They should be connected directly to each other under the part to reduce potential noise problems.
A 1- µ F tantalum capacitor is recommended as an ac-coupling capacitor, which establishes a 5.3-Hz cutoff
frequency. If a higher full-scale input voltage is required, the input voltage range can be increased by adding a
series resistor to the V
IN
pins.
A 4.7- µ F tantalum capacitor is recommended between V
REF
1, V
REF
2, and REFCOM to ensure low source
impedance for the ADC references. These capacitors should be located as close as possible to the V
REF
1 and
V
REF
2 pins to reduce dynamic errors on the ADC references. The REFCOM pin also should be connected
directly to AGND under the part.
A 470-pF to 1000-pF film capacitor is recommended between C
IN
PL and C
IN
NL, C
IN
PR and C
IN
NR to create an
antialiasing filter which has a 170-kHz to 80-kHz cutoff frequency. These capacitors should be located as close
as possible to the C
IN
P and C
IN
N pins to avoid introducing unexpected noise or dynamic errors into the
delta-sigma modulator. Four 10-pF – 47-pF capacitors between C
IN
XX and AGND may improve dynamic
performance under disadvantageous actual conditions.
In master mode, the DOUT, BCK, LRCK and FSYNC pins have a large load-drive capability, but locating the
buffer near the PCM1800 and minimizing the load capacitance is recommended in order to minimize the
digital-analog crosstalk and to maximize dynamic performance potential.
The quality of the system clock can influence dynamic performance in the PCM1800. The duty cycle, jitter, and
threshold voltage at the system clock input pin must be carefully managed. When power is supplied to the part,
the system clock, bit clock (BCK), and word clock (LRCK) should also be supplied simultaneously. Failure to
supply the audio clocks results in a power dissipation increase of up to three times normal dissipation and can
degrade long-term reliability if the maximum power dissipation limit is exceeded.
If the capacitance between V
REF
1 and V
REF
2 exceeds 4.7 µ F, an external reset control with a delay-time circuit
must be used.
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Product Folder Link(s): PCM1800