Datasheet

BCK
FSYNC
LRCK
DOUT
t
(CKFS)
t
(BCKH)
t
(BCKL)
t
(CKLR)
t
(LRCP)
t
(BCKP)
t
(CKDO)
t
(LRDO)
0.5 V
DD
0.5 V
DD
0.5 V
DD
0.5 V
DD
t
(FSYP)
T0018-01
SYNCHRONIZATION WITH DIGITAL AUDIO SYSTEM
ADC DATA OUTPUT AT RESET
PCM1800
SBAS071B – OCTOBER 2000 – REVISED AUGUST 2008 ............................................................................................................................................... www.ti.com
DESCRIPTION SYMBOL MIN TYP MAX UNITS
BCK period t
(BCKP)
300 1/64 f
S
4800 ns
BCK pulse duration, HIGH t
(BCKH)
150 2400 ns
BCK pulse duration, LOW t
(BCKL)
150 2400 ns
Delay time, BCK falling edge to LRCK valid t
(CKLR)
– 20 40 ns
LRCK period t
(LRCP)
20 1/f
S
320 µ s
Delay time, BCK falling edge to FSYNC valid t
(CKFS)
– 20 40 ns
FSYNC period t
(FSYP)
10 1/2 f
S
160 µ s
Delay time, BCK falling edge to DOUT valid t
(CKDO)
– 20 40 ns
Delay time, LRCK edge to DOUT valid t
(LRDO)
– 20 40 ns
Rising time of all signals t
(RISE)
20 ns
Falling time of all signals t
(FALL)
20 ns
NOTE: Timing measurement reference level is (V
IH
+ V
IL
)/2. Rising and falling time is measured from 10% to 90% of the I/O
signal swing. Load capacitance of the DOUT signal is 20 pF.
Figure 25. Audio Data Interface Timing (Master Mode: FSYNC, LRCK, and BCK Are Outputs)
In slave mode, the PCM1800 operates with LRCK synchronized to the system clock (SYSCLK). The PCM1800
does not require a specific phase relationship between LRCK and SYSCLK, but does require the synchronization
of LRCK and SYSCLK. If the relationship between LRCK and SYSCLK changes more than 6 bit clocks (BCK)
during one sample period due to LRCK or SYSCLK jitter, internal operation of the ADC halts within 1/f
S
and the
digital output is forced into the BPZ mode until resynchronization between LRCK and SYSCLK is completed. In
case of changes less than 5 bit clocks (BCK), resynchronization does not occur, and the previously described
digital output control and discontinuity does not occur.
Figure 26 and Figure 27 illustrate the ADC digital output when the reset operation is done and when
synchronization is lost, respectively. During undefined data, some noise may be generated in the audio signal.
Also, the transition of normal to undefined data and undefined or zero data to normal makes a discontinuity in the
data on the digital output, and may generate some noise in the audio signal.
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Product Folder Link(s): PCM1800