Datasheet

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SLES102A – DECEMBER 2003 – REVISED NOVEMBER 2006
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Audio Format
The PCM1798 in the external digital filter interface mode supports the 24-bit right-justified audio format as shown
in Figure 27.
BCK
1/4 f
S
or 1/8 f
S
WDCK
Audio Data Word = 24-Bit
MSB LSB
161 2 3 4 5 6 7 8 9 10 11 12 13 14 152423 2017 18 19 2421 22 23
DATA
Figure 27. Audio Data Input Format for External Digital Filter (Internal DF Bypass Mode) Application
System Clock (SCK) and Interface Timing
The PCM1798 in an application using an external digital filter requires the synchronization of WDCK and the system
clock. The system clock is phase-free with respect to WDCK. Interface timing among WDCK, BCK, and DATA is
shown in Figure 28.
DATA
t
(BCH)
1.4 V
BCK
WDCK
t
(BCL)
t
(LB)
t
(BCY)
t
(DS)
t
(DH)
1.4 V
1.4 V
t
(BL)
PARAMETER MIN MAX UNITS
t
(BCY)
BCK pulse cycle time 20 ns
t
(BCL)
BCK pulse duration, LOW 7 ns
t
(BCH)
BCK pulse duration, HIGH 7 ns
t
(BL)
BCK rising edge to WDCK falling edge 5 ns
t
(LB)
WDCK falling edge to BCK rising edge 5 ns
t
(DS)
DATA setup time 5 ns
t
(DH)
DATA hold time 5 ns
Figure 28. Audio Interface Timing for External Digital Filter (Internal DF Bypass Mode) Application