Datasheet

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SLES102A – DECEMBER 2003 – REVISED NOVEMBER 2006
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21
APPLICATION FOR EXTERNAL DIGITAL FILTER INTERFACE
DATA
24
23
22
21
20
19
18
17
16
15
5
6
7
8
9
10
11
12
13
14
PCM1798
BCK
SCK
DGND
V
DD
MUTE
FMT0
FMT1
ZERO
RST
AGND2
I
OUT
R–
V
CC
1
V
COM
L
V
COM
R
I
REF
I
OUT
R+
AGND3R
AGND1
MONO
1
2
3
4
CHSL
DEM
LRCK
28
27
26
25
V
CC
2L
AGND3L
I
OUT
L–
I
OUT
L+
V
CC
2R
DATA
Analog
Output Stage
(See Figure 23)
WDCK
BCK
SCK
External
Filter
Device
V
DD
Figure 26. Connection Diagram for External DIgital Filter (Internal DF Bypass Mode) Application
Application for Interfacing With an External Digital Filter
For some applications, it may be desirable to use a programmable digital signal processor as an external digital filter
to perform the interpolation function. The following pin settings enable the external digital filter application mode.
D MONO (pin 1) = LOW
D CHSL (Pin 2) = HIGH
D FMT0 (Pin 11) = HIGH
D FMT1 (pin 12) = HIGH
The pins used to provide the serial interface for the external digital filter are shown in the connection diagram of
Figure 26. The word clock (WDCK) must be operated at 8× or 4× the desired sampling frequency, f
S
.
Pin Assignment When Using the External Digital Filter Interface
D LRCK (pin 4): WDCK as word clock input
D DATA (pin 5): Monaural audio data input
D BCK (pin 6): Bit clock input