Datasheet

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SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006
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42
Requirements for System Clock
For operation in the DSD mode, the bit clock (DBCK) is required on pin 7 of the PCM1796. The frequency of the bit
clock can be N times the sampling frequency. Generally, N is 64 in DSD applications.
The interface timing between the bit clock and DSDL and DSDR is required to meet the setup and hold time
specifications shown in Figure 44.
t = 1/(64 × 44.1 kHz)
D1
DSDL
DSDR
D0 D2 D3 D4
DBCK
Figure 43. Normal Data Output Form From DSD Decoder
DSDL
DSDR
t
(BCH)
DBCK
t
(BCL)
t
(BCY)
1.4 V
1.4 V
t
(DS)
t
(DH)
PARAMETER MIN MAX UNITS
t
(BCY)
DBCK pulse cycle time 85
(1)
ns
t
(BCH)
DBCK high-level time 30 ns
t
(BCL)
DBCK low-level time 30 ns
t
(DS)
DSDL, DSDR setup time 10 ns
t
(DH)
DSDL, DSDR hold time 10 ns
(1)
2.8224 MHz × 4. (2.8224 MHz = 64 × 44.1 kHz. This value is
specified as a sampling rate of DSD.)
Figure 44. Timing for DSD Audio Interface