Datasheet

FUNCTIONS AVAILABLE IN THE EXTERNAL DIGITAL FILTER MODE
FMT[2:0]: Audio Data Format Selection
OS[1:0]: Δ Σ Modulator Oversampling Rate Selection
PCM1795
SLES248 – MAY 2009 ........................................................................................................................................................................................................ www.ti.com
The external digital filter mode is selected by setting DSD = 0 (register 20, B5) and DFTH = 1 (register 20, B4).
The external digital filter mode allows access to the majority of the PCM1795 mode control functions.
Table 12 shows the register mapping available when the external digital filter mode is selected, along with
descriptions of functions that are modified when using this mode selection.
Table 12. External Digital Filter Register Map
REGISTER B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Register 16 R/ W 0 0 1 0 0 0 0 X
(1)
X X X X X X X
Register 17 R/ W 0 0 1 0 0 0 1 X X X X X X X X
Register 18 R/ W 0 0 1 0 0 1 0 X FMT2 FMT1 FMT0 X X X X
Register 19 R/ W 0 0 1 0 0 1 1 REV X X OPE X DFMS X INZD
Register 20 R/ W 0 0 1 0 1 0 0 X SRST 0 1 MONO CHSL OS1 OS0
Register 21 R/ W 0 0 1 0 1 0 1 X X X X X X X PCMZ
Register 22 R 0 0 1 0 1 1 0 X X X X X X ZFGR ZFGL
(1) Function is disabled. No operation even if data bit is set.
Default value: 000
FMT[2:0] Audio Data Format Selection
000 16-bit right-justified format
001 32-bit right-justified format
010 24-bit right-justified format (default)
Other N/A
Default value: 00
OS[1:0] Operation Speed Selection
00 8 times WDCK (default)
01 4 times WDCK
10 16 times WDCK
11 Reserved
The effective oversampling rate is determined by the oversampling performed by both the external digital filter
and the Δ Σ modulator. For example, if the external digital filter is 8 × oversampling, and OS[1:0] = 00 is selected,
then the Δ Σ modulator oversamples by 8 × , resulting in an effective oversampling rate of 64 × . The 16 × WDCK
oversampling rate is not available above a 100-kHz sampling rate. If the oversampling rate selected is 16 ×
WDCK, the system clock frequency must be over 256 f
S
.
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