Datasheet

System Clock (SCK) and Interface Timing
t
(BCH)
BCK
WDCK
t
(BCL)
t
(LB)
t
(BCY)
t
(DS)
t
(DH)
1.4 V
1.4V
t
(BL)
1.4V
DATA
DATAL
DATAR
PCM1795
www.ti.com ........................................................................................................................................................................................................ SLES248 – MAY 2009
The PCM1795 in an application using an external digital filter requires the synchronization of WDCK and the
system clock. The system clock is phase-free with respect to WDCK. Interface timing among WDCK, BCK,
DATA, DATAL, and DATAR is shown in Figure 57 and Table 11 .
Figure 57. Audio Interface Timing for External Digital Filter (Internal DF Bypass Mode) Application
Table 11. Timing Characteristics for Figure 57
PARAMETER MIN MAX UNIT
t
(BCY)
BCK pulse cycle time 20 ns
t
(BCL)
BCK pulse duration, low 7 ns
t
(BCH)
BCK pulse duration, high 7 ns
t
(BL)
BCK rising edge to WDCK falling edge 5 ns
t
(LB)
WDCK falling edge to BCK rising edge 5 ns
t
(DS)
DATA, DATAL, DATAR setup time 5 ns
t
(DH)
DATA, DATAL, DATAR hold time 5 ns
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Product Folder Link(s): PCM1795