Datasheet

Register 21
R/W
0 0
1
0 1 0
1
RSV
RSV RSV
RSV
RSV
DZ1 DZ0
PCMZ
B15
B14 B13
B12
B11 B10 B9
B8
B7
B6 B5
B4
B3
B2 B1
B0
Register 22
R
0 0
1
0 1 1
0
RSV
RSV RSV
RSV
RSV
RSV ZFGR
ZFGL
B15
B14 B13
B12
B11 B10 B9
B8
B7
B6 B5
B4
B3
B2 B1
B0
PCM1795
SLES248 – MAY 2009 ........................................................................................................................................................................................................ www.ti.com
R/ W: Read/Write Mode Select
When R/ W = 0, a write operation is performed.
When R/ W = 1, a read operation is performed.
Default value: 0
DZ[1:0]: DSD Zero Output Enable
These bits are available for read and write.
Default value: 00
DZ[1:0] Zero Output Enable
00 Disabled (default)
01 Even pattern detect 1 × 96h pattern detect
The DZ bits are used to enable or disable the output zero flags and to select the zero pattern in DSD mode.
PCMZ: PCM Zero Output Enable
These bits are available for read and write.
Default value: 1
PCMZ PCM Zero Output Setting
PCMZ = 0 PCM zero output disabled
PCMZ = 1 PCM zero output enabled (default)
The PCMZ bit is used to enable or disable the output zero flags in PCM mode and the external DF mode.
R: Read Mode Select
Value is always '1', specifying the readback mode.
ZFGx: Zero-Detection Flag
Where x = L or R, corresponding to the DAC output channel. These bits are available only for readback.
Default value: 00
ZFGx Zero Detection
ZFGx = 0 Not zero
ZFGx = 1 Zero detected
These bits show zero conditions. The status is the same as that of the zero flags at ZEROL (pin 1) and ZEROR
(pin 2). See Zero Detect in the Function Descriptions section.
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